Datasheet > FMS9884A

FMS9884A

更新时间： 2022-11-04 17:13:26

品牌	Logo	应用领域
飞兆/仙童 - FAIRCHILD		转换器
页数	文件大小	规格书
29页	235K
描述
3x8-Bit, 108/140/175 Ms/s Triple Video A/D Converter with Clamps

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FMS9884A 数据手册

www.fairchildsemi.com

FMS9884A

Graphics Digitizer

3x8-Bit, 108/140/175 Ms/s Triple Video A/D Converter with Clamps

is via registers, accessible through an SMBus/I²C compatible

serial port.

Features

• 3-channels

• 100/140/175 Ms/s conversion rate

• Programmable Clamps

• Adjustable Gain and offset

Input amplitude range is 500–1000mV with either DC or AC

coupling. Lower reference of AC coupled inputs is estab-

lished with input clamps that are either internally generated

or externally provided.

• Internal Reference Voltage

• I²C/SMBus compatible Serial Port

• Pin Compatible with AD9884A

Common to the three channels are clamp pulses, a bandgap

reference voltage and clocks derived from a PLL or an external

source. Digital data levels are 2.5–3.3 volt CMOS compliant.

Applications

• Flat panel displays and projectors

Power can be derived from a single +3.3 Volt power supply. For

• RGB Graphics Processing

175 MHz applications see special V_PLLrequirements. Package

is a 128-lead MQFP. Performance speciﬁcations are guaran-

teed over 0°C to 70°C range.

Description

As a fully integrated analog interface, the FMS9884A can digi-

tize RGB graphics with resolutions up to 1600 x 1200/65Hz

Product Number

FMS9884AKAC100

FMS9884AKAC140

FMS9884AKAC175

Speed

refresh or 1600 x 1200/85Hz using alternate pixel sampling.

ADC sampling clock can be derived from either an external

source or incoming horizontal sync signal using the internal

PLL. Output data is released through either one port at full

rate or both ports, each running at half-rate. Setup and control

108 Ms/s

140 Ms/s

175 Ms/s

Block Diagram

RPD_7-0

DRA_7-0

A/D

Converter

Gain &

Offset

Clamp

R_IN

Switch

DRB_7-0

GPD_7-0

BPD_7-0

DGA_7-0

DGB_7-0

Gain &

Offset

A/D

Converter

G_IN

DBA_7-0

DBB_7-0

Gain &

Offset

A/D

Converter

B_IN

Reference

VREFIN

VREFOUT

SCK

CLAMP

INVSCK

XCK

ICLAMP

DCK

HSOUT

Timing

Generator

PXCK

HSIN

COAST

LPF

PLL

SDA

SCL

A₀

A₁

SYNC

STRIPPER

ACS_IN

Control

DCS_OUT

PWRDN

REV. 1.2.2 12/7/01

12 3 4 5 6 7...29

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