Datasheet > FMS988AKAC100

FMS988AKAC100

更新时间： 2024-11-19 23:52:27

品牌	Logo	应用领域
其他 - ETC		/
页数	文件大小	规格书
29页	374K
描述
Signal Conditioner

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数据手册

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FMS988AKAC100 数据手册

www.fairchildsemi.com

FMS9884A

Graphics Digitizer

3x8-Bit, 108/140 Ms/s Triple Video A/D Converter with Clamps

PLL. Output data is released through either one port at full

Features

rate or both ports, each running at half-rate. Setup and control

is via registers, accessible through an SMBus/I²C compatible

• 3-channels

• 100/140 Ms/s conversion rate

serial port.

• Programmable Clamps

• 500ps PLL clock jitter

• Adjustable Gain and offset

Input amplitude range is 500–1000mV with either DC or AC

coupling. Lower reference of AC coupled inputs is estab-

lished with input clamps that are either internally generated

or externally provided.

• Internal Reference Voltage

• I²C/SMBus compatible Serial Port

• Pin Compatible with AD9884A

Common to the three channels are clamp pulses, a bandgap

reference voltage and clocks derived from a PLL or an external

source. Digital data levels are 2.5–3.3 volt CMOS compliant.

Applications

• Flat panel displays and projectors

• RGB Graphics Processing

Power can be derived from a single +3.3 Volt power supply.

Package is a 128-lead MQFP. Performance speciﬁcations are

guaranteed over 0°C to 70°C range.

Description

As a fully integrated analog interface, the FMS9884A can digi-

tize RGB graphics with resolutions up to 1280 x 1024/75Hz

refresh or 1600 x 1200/85Hz using alternate pixel sampling.

ADC sampling clock can be derived from either an external

source or incoming horizontal sync signal using the internal

Product Number

FMS988AKAC100

FMS988AKAC140

Speed

108 Ms/s

140 Ms/s

Block Diagram

RPD_7-0

DRA_7-0

A/D

Converter

Gain &

Offset

Clamp

R_IN

Switch

DRB_7-0

GPD_7-0

BPD_7-0

DGA_7-0

DGB_7-0

Gain &

Offset

A/D

Converter

G_IN

DBA_7-0

DBB_7-0

Gain &

Offset

A/D

Converter

B_IN

Reference

VREFIN

VREFOUT

SCK

CLAMP

INVSCK

XCK

ICLAMP

DCK

HSOUT

Timing

Generator

PXCK

HSIN

COAST

LPF

PLL

SDA

SCL

A₀

A₁

SYNC

STRIPPER

ACS_IN

Control

DCS_OUT

PWRDN

REV. 1.0.2 8/11/00

12 3 4 5 6 7...29

中文翻译

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