Datasheet > FMS9875KGC140X

FMS9875KGC140X

更新时间： 2024-11-19 23:52:27

品牌	Logo	应用领域
其他 - ETC		转换器
页数	文件大小	规格书
29页	482K
描述

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数据手册

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FMS9875KGC140X 数据手册

www.fairchildsemi.com

FMS9875

GBR YP P Graphics Digitizer

B R

Triple 8-Bit, 108/140 MHz A/D Converter with Clamps and PLL

The ADC sampling clock can be derived from either an

external source or from incoming horizontal sync using the

Features

• 108/140 Ms/s conversion rate

• RGB and YP_BP_Rclamps

• 444 and 422 output timing

• Adjustable Gain and offset

• Internal Reference Voltage

• I²C/SMBus compatible Serial Port

• 100-pin package

internal PLL. Setup and control is via registers accessible

through an SMBus/I²C compatible serial port.

Input amplitude range is 500–1000mV with either DC or AC

coupling. AC coupled inputs can be clamped to program-

mable midpoint/bottom levels or to external reference levels

using either internal or externally generated clamp timing.

Common to the three channels are clamp pulses, a bandgap

reference voltage and clocks derived from the HSYNC PLL

or an external clock source. Digital data output levels are

2.5–3.3V CMOS compliant.

Applications

• YP_BP_RDigitizers

• Projectors

• TV sets

Power is derived from a single +3.3 Volt power supply. Package

is a low cost 100-lead MQFP. Performance speciﬁcations are

guaranteed over 0°C to 70°C.

Description

As a fully integrated graphics interface, the FMS9875 can

digitize RGB orYP_BP_Rvideo signals at resolutions up to

1280 x 1024 with 75 Hz refresh rate. Compatible video

formats include NTSC-601, PAL-601, SMPTE 293M,

SMPTE 296M and SMPTE 274M.

Product Number

FMS9875KAC100

FMS9875KAC140

Speed

108 Ms/s

140 Ms/s

Block Diagram

GY_IN

Gain &

Offset

Bottom

Clamp

DGY_7-0

A/D

GY_REF

Bottom/

Midpoint

Clamp

BP_IN

Gain &

Offset

444/422

A/D

DBP_7-0

DRP_7-0

BP_REF

Bottom/

Midpoint

Clamp

RP_IN

Gain &

Offset

444/422

RP_REF

ICLAMP

VREFIN

Reference

VREFOUT

SCK

CLAMP

INVSCK

XCK

ICLAMP

Timing

Generator

DCK

HSOUT

PXCK

HSIN

COAST

LPF

PLL

SDA

SCL

A₀

A₁

SYNC

Stripper

ACS_IN

DCS_OUT

Control

PWRDN

REV. 1.2.15 1/14/02

12 3 4 5 6 7...29

中文翻译

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