FM25V10
setting the WPEN, BP0 and BP1 bits as required. Before issuing
a WRSR command, the WP pin must be HIGH or inactive. Note
that on the FM25V10, WP only prevents writing to the Status
Register, not the memory array. Before sending the WRSR
command, the user must send a WREN command to enable
writes. Executing a WRSR command is a write operation and
therefore, clears the Write Enable Latch.
RDSR - Read Status Register
The RDSR command allows the bus master to verify the
contents of the Status Register. Reading the status register
provides information about the current state of the
write-protection features. Following the RDSR opcode, the
FM25V10 will return one byte with the contents of the Status
Register.
WRSR - Write Status Register
The WRSR command allows the SPI bus master to write into the
Status Register and change the write protect configuration by
Figure 9. RDSR Bus Configuration
CS
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
SCK
Opcode
SI
0
0
0
0
0
1
0
1
0
Data
D7 D6 D5 D4 D3 D2 D1 D0
MSB LSB
HI-Z
SO
Figure 10. WRSR Bus Configuration (WREN not shown)
CS
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
SCK
Data
Opcode
SI
1
0
0
0
0
0
0
0
D7
MSB
X
X
X
D3 D2
X
X
LSB
HI-Z
SO
the last address of 1FFFFh is reached, the counter will roll over
to 00000h. Data is written MSB first. The rising edge of CS
terminates a write operation. Awrite operation is shown in Figure
11.
Memory Operation
The SPI interface, which is capable of a high clock frequency,
highlights the fast write capability of the F-RAM technology.
Unlike serial flash and EEPROMs, the FM25V10 can perform
sequential writes at bus speed. No page register is needed and
any number of sequential writes may be performed.
Note When a burst write reaches a protected block address, the
automatic address increment stops and all the subsequent data
bytes received for write will be ignored by the device.
Write Operation
EEPROMs use page buffers to increase their write throughput.
This compensates for the technology's inherently slow write
operations. F-RAM memories do not have page buffers because
each byte is written to the F-RAM array immediately after it is
clocked in (after the eighth clock). This allows any number of
bytes to be written without page buffer delays.
All writes to the memory begin with a WREN opcode with CS
being asserted and deasserted. The next opcode is WRITE. The
WRITE opcode is followed by a three-byte address containing
the 17-bit address (A16-A0) of the first data byte to be written into
the memory. Subsequent bytes are data bytes, which are written
sequentially. Addresses are incremented internally as long as
the bus master continues to issue clocks and keeps CS LOW. If
Note If the power is lost in the middle of the write operation, only
the last completed byte will be written.
Document Number: 001-84499 Rev. *H
Page 8 of 25
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