Datasheet > FM25VN10-GTR

FM25VN10-GTR

更新时间： 2024-03-03 10:08:51

品牌	Logo	应用领域
英飞凌 - INFINEON		存储
页数	文件大小	规格书
25页	2492K
描述
铁电存储器 (F-RAM)

阅读下载

获取价格

数据手册

如果您发现信息不准确，欢迎纠错

FM25VN10-GTR 数据手册

FM25V10

For a microcontroller that has no dedicated SPI bus, a

general-purpose port may be used. To reduce hardware

resources on the controller, it is possible to connect the two data

pins (SI, SO) together and tie off (HIGH) the HOLD and WP pins.

Figure 4 shows such a configuration, which uses only three pins.

these bits be set to 0s to enable seamless transition to higher

memory densities.

Serial Opcode

After the slave device is selected with CS going LOW, the first

byte received is treated as the opcode for the intended operation.

FM25V10 uses the standard opcodes for memory accesses.

Most Significant Bit (MSB)

The SPI protocol requires that the first bit to be transmitted is the

Most Significant Bit (MSB). This is valid for both address and

data transmission.

Invalid Opcode

If an invalid opcode is received, the opcode is ignored and the

device ignores any additional serial data on the SI pin until the

next falling edge of CS, and the SO pin remains tristated.

The 1-Mbit serial F-RAM requires a 3-byte address for any read

or write operation. Because the address is only 17 bits, the first

seven bits, which are fed in are ignored by the device. Although

these seven bits are ‘don’t care’, Cypress recommends that

Status Register

FM25V10 has an 8-bit Status Register. The bits in the Status

described in Table 3 on page 7.

Figure 3. System Configuration with SPI Port

SCK

MOSI

MISO

SCK

SI SO

SPI

Microcontroller

FM25V10

HOLD WP

C S 1

H O LD 1

W P 1

C S 2

H O LD 2

W P 2

Figure 4. System Configuration without SPI Port

P1.0

P1.1

SCK

SI SO

Microcontroller

FM25V10

HOLD WP

P1.2

For both these modes, the input data is latched in on the rising

SPI Modes

edge of SCK starting from the first rising edge after CS goes

active. If the clock starts from a HIGH state (in mode 3), the first

rising edge after the clock toggles is considered. The output data

is available on the falling edge of SCK.

FM25V10 may be driven by a microcontroller with its SPI

peripheral running in either of the following two modes:

■ SPI Mode 0 (CPOL = 0, CPHA = 0)

■ SPI Mode 3 (CPOL = 1, CPHA = 1)

Document Number: 001-84499 Rev. *H

Page 5 of 25

1 2 3 456 7 8...25

下载PDF

与FM25VN10-GTR相关器件

型号	品牌	描述	获取价格	数据表
FM25W01	FM	SPI NOR Flash	获取价格
FM25W02	FM	SPI NOR Flash	获取价格
FM25W04	FM	SPI NOR Flash	获取价格
FM25W16	FM	SPI NOR Flash	获取价格
FM25W256	RAMTRON	256Kb Wide Voltage SPI F-RAM	获取价格
FM25W256_13	CYPRESS	256Kb Wide Voltage SPI F-RAM	获取价格