FM25V10
Pinouts
Figure 1. 8-pin SOIC pinout
8
7
6
5
V
CS
SO
1
2
3
DD
HOLD
SCK
SI
Top View
not to scale
WP
V
4
SS
Figure 2. 8-pin DFN pinout
O
V
CS
SO
WP
8
7
6
5
1
2
3
4
DD
HOLD
SCK
SI
EXPOSED
PAD
V
SS
Top View
not to scale
Pin Definitions
Pin Name
I/O Type
Description
CS
Input
Chip Select. This active LOW input activates the device. When HIGH, the device enters low-power
standby mode, ignores other inputs, and the output is tristated. When LOW, the device internally
activates the SCK signal. A falling edge on CS must occur before every opcode.
SCK
Input
Serial Clock. All I/O activity is synchronized to the serial clock. Inputs are latched on the rising edge
and outputs occur on the falling edge. Because the device is synchronous, the clock frequency may
be any value between 0 and 40 MHz and may be interrupted at any time.
SI [1]
SO [1]
WP
Input
Output
Input
Serial Input. All data is input to the device on this pin. The pin is sampled on the rising edge of SCK
and is ignored at other times. It should always be driven to a valid logic level to meet IDD specifications.
Serial Output. This is the data output pin. It is driven during a read and remains tristated at all other
times including when HOLD is LOW. Data transitions are driven on the falling edge of the serial clock.
Write Protect. This Active LOW pin prevents write operation to the Status Register when WPEN is
set to ‘1’. This is critical because other write protection features are controlled through the Status
Register. Acomplete explanation of write protection is provided in Status Register and Write Protection
on page 7. This pin must be tied to VDD if not used.
HOLD
Input
HOLD Pin. The HOLD pin is used when the host CPU must interrupt a memory operation for another
task. When HOLD is LOW, the current operation is suspended. The device ignores any transition on
SCK or CS. All transitions on HOLD must occur while SCK is LOW. This pin has a weak internal pull-up
(Refer DC Electrical Characteristics table for RIN spec). However, if it is not used, the HOLD pin should
be tied to VDD
.
VSS
VDD
Power supply Ground for the device. Must be connected to the ground of the system.
Power supply Power supply input to the device.
EXPOSED
PAD
No connect The EXPOSED PAD on the bottom of 8-pin DFN package is not connected to the die. The EXPOSED
PAD should not be soldered on the PCB.
Note
1. SI may be connected to SO for a single pin data interface.
Document Number: 001-84499 Rev. *H
Page 3 of 25
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