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FM25VN05-GTR PDF预览

FM25VN05-GTR

更新时间： 2024-01-11 06:22:12
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 存储
页数 文件大小 规格书
16页 532K
描述
512Kb Serial 3V F-RAM Memory

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中文翻译

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FM25VN05-GTR 技术参数

是否Rohs认证： 符合生命周期：Obsolete
零件包装代码：SOIC包装说明：SOP,
针数：8Reach Compliance Code：unknown
HTS代码：8542.32.00.71风险等级：5.82
JESD-30 代码：R-PDSO-G8JESD-609代码：e3
长度：4.9 mm内存密度：524288 bit
内存集成电路类型：MEMORY CIRCUIT内存宽度：8
湿度敏感等级：1功能数量：1
端子数量：8字数：65536 words
字数代码：64000工作模式：SYNCHRONOUS
最高工作温度：85 °C最低工作温度：-40 °C
组织：64KX8封装主体材料：PLASTIC/EPOXY
封装代码：SOP封装形状：RECTANGULAR
封装形式：SMALL OUTLINE峰值回流温度（摄氏度）：260
认证状态：Not Qualified座面最大高度：1.75 mm
最大供电电压 (Vsup)：3.6 V最小供电电压 (Vsup)：2 V
标称供电电压 (Vsup)：3.3 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子面层：Matte Tin (Sn)端子形式：GULL WING
端子节距：1.27 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：3.9 mm

FM25VN05-GTR 数据手册

 浏览型号FM25VN05-GTR的Datasheet PDF文件第2页浏览型号FM25VN05-GTR的Datasheet PDF文件第3页浏览型号FM25VN05-GTR的Datasheet PDF文件第4页浏览型号FM25VN05-GTR的Datasheet PDF文件第6页浏览型号FM25VN05-GTR的Datasheet PDF文件第7页浏览型号FM25VN05-GTR的Datasheet PDF文件第8页 
FM25V05 - 512Kb SPI FRAM  
clear the write-enable latch and prevent further  
writes without another WREN command. Figure 5  
below illustrates the WREN command bus  
configuration.  
Power Up to First Access  
The FM25V05 is not accessible for a period of time  
(tPU) after power up. Users must comply with the  
timing parameter tPU, which is the minimum time  
from VDD (min) to the first /S low.  
S
Data Transfer  
0
0
1
0
2
0
3
0
4
0
5
1
6
1
7
0
All data transfers to and from the FM25V05 occur in  
8-bit groups. They are synchronized to the clock  
signal (C), and they transfer most significant bit  
(MSB) first. Serial inputs are registered on the rising  
edge of C. Outputs are driven from the falling edge of  
clock C.  
C
D
Q
Hi-Z  
Command Structure  
There are ten commands called op-codes that can be  
issued by the bus master to the FM25V05. They are  
listed in the table below. These op-codes control the  
functions performed by the memory. They can be  
divided into three categories. First, there are  
commands that have no subsequent operations. They  
perform a single function, such as to enable a write  
operation. Second are commands followed by one  
byte, either in or out. They operate on the Status  
Register. The third group includes commands for  
memory transactions followed by address and one or  
more bytes of data.  
Figure 5. WREN Bus Configuration  
WRDI – Write Disable  
The WRDI command disables all write activity by  
clearing the Write Enable Latch. The user can verify  
that writes are disabled by reading the WEL bit in  
the Status Register and verifying that WEL=0.  
Figure 6 illustrates the WRDI command bus  
configuration.  
S
Table 1. Op-code Commands  
0
0
1
0
2
0
3
4
5
1
6
0
7
0
Name  
WREN  
WRDI  
RDSR  
WRSR  
READ  
FSTRD  
WRITE  
SLEEP  
RDID  
Description  
Set Write Enable Latch  
Write Disable  
Read Status Register  
Write Status Register  
Read Memory Data  
Fast Read Memory Data  
Write Memory Data  
Enter Sleep Mode  
Read Device ID  
Op-code  
C
00000110b  
00000100b  
00000101b  
00000001b  
00000011b  
00001011b  
00000010b  
10111001b  
10011111b  
11000011b  
0
0
D
Q
Hi-Z  
Figure 6. WRDI Bus Configuration  
Read S/N  
SNR  
RDSR – Read Status Register  
The RDSR command allows the bus master to  
verify the contents of the Status Register. Reading  
Status provides information about the current state  
of the write protection features. Following the  
RDSR op-code, the FM25V05 will return one byte  
with the contents of the Status Register. The Status  
Register is described in detail in the section below.  
WREN – Set Write Enable Latch  
The FM25V05 will power up with writes disabled.  
The WREN command must be issued prior to any  
write operation. Sending the WREN op-code will  
allow the user to issue subsequent op-codes for write  
operations. These include writing the Status Register  
(WRSR) and writing the memory (WRITE).  
Sending the WREN op-code causes the internal Write  
Enable Latch to be set. A flag bit in the Status  
Register, called WEL, indicates the state of the latch.  
WEL=1 indicates that writes are permitted.  
Attempting to write the WEL bit in the Status  
Register has no effect on the state of this bit.  
Completing any write operation will automatically  
Rev. 3.0  
Jan. 2012  
Page 5 of 16  
12345678...16

中文翻译

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