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FLIPCHIP11 PDF预览

FLIPCHIP11

更新时间: 2024-10-25 22:28:31
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 转换器电平转换器
页数 文件大小 规格书
11页 476K
描述
4-BIT DUAL SUPPLY BUS BUFFER LEVEL TRANSLATOR WITH A SIDE SERIES RESISTOR

FLIPCHIP11 数据手册

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ST4G3234  
4-BIT DUAL SUPPLY BUS BUFFER LEVEL TRANSLATOR  
WITH A SIDE SERIES RESISTOR  
I
I
I
HIGH SPEED: t = 4.4ns (MAX.) at T =85°C  
PD A  
V
= 1.65V; V  
= 3.0V  
CCB  
CCA  
LOW POWER DISSIPATION:  
= I = 5µA(MAX.) at T =85°C  
I
CCA  
CCB  
A
SYMMETRICAL OUTPUT IMPEDANCE:  
|I | = I = 10mA MIN at  
OHA  
OLA  
V
= 3.0V; V  
= 1.4V to 3.6V  
CCA  
OHA  
CCB  
FLIPCHIP  
|I  
V
| = I  
= 8mA MIN at  
OLA  
= 2.3V; V  
= 1.4 to 3.6V)  
CCB  
CCA  
Table 1: Order Codes  
I
I
BALANCED PROPAGATION DELAYS:  
t  
POWER DOWN PROTECTION ON INPUTS  
AND OUTPUTS  
t
PLH  
PHL  
PACKAGE  
T & R  
ST4G3234BJR  
Comments  
FLIPCHIP11  
5000 parts per reel  
I
I
26SERIESRESISTORONASIDEOUTPUTS  
All inputs are equipped with protection circuits  
against static discharge, giving them ESD immuni-  
ty and transient excess voltage.  
OPERATING VOLTAGE RANGE:  
V
(OPR) = 1.4V to 3.6V (1.2V Data Retent)  
(OPR) = 1.4V to 3.6V (1.2V Data Retent)  
CCA  
CCB  
V
I
MAX DATA RATES:  
Figure 1: Logic Diagram  
380 Mbps (1.8V to 3.3V translation)  
260 Mbps (<1.8V to 3.3V translation)  
260 Mbps (Translate to 2.5V)  
210 Mbps (Translate to 1.5V)  
100 Mbps (Translate to 1.2V)  
I
I
LATCH-UP PERFORMANCE EXCEEDS  
500mA (JESD 17)  
ESD PERFORMANCE:  
HBM > 2000V (MIL STD 883 method 3015);  
MM > 200V  
I
R HS Compliant for FLIPCHIP Package  
O
DESCRIPTION  
The ST4G3234 is a dual supply low voltage  
CMOS 4-BIT BUS BUFFER level translator  
fabricated with sub-micron silicon gate and  
2
five-layer metal wiring C MOS technology.  
Designed for use as an interface between a 3.3V  
bus and a 2.5V or 1.8V bus in a mixed 3.3V/1.8V,  
3.3V/2.5V, 1.8V/1.4V and 2.5V/1.8V supply  
systems, it achieves high speed operation while  
maintaining the CMOS low power dissipation.  
This IC is intended for one-way asynchronous  
communication between data buses. The input  
and output power down protections disable the  
device when both power supply are down, so that  
the buses are effectively isolated.  
The input tolerant buffers allow to translate V  
compatible signals and greater signals than V  
CCB  
CCB  
up/down to V  
.
CCA  
Rev. 7  
1/11  
May 2005  

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