Intel® IXF3204 Quad T1/E1/J1 Framer
with Intel® On-Chip PRM
Datasheet
Product Features
■ Quad T1/E1/J1 Framer
■ Diagnostics:
■ Software selectable and fully independent
—BERT generators and analyzers for
extensive on-chip error testing at DS-0,
DS-1, and E1 rates
T1/E1/J1 operation
■ Support for T1/E1/J1 standards:
—T1: T1-SF, T1-ESF, Lucent* SLC®96
—Pseudo-random and programmable bit-
—E1: PCM30, G.704, G.706, G.732 ISDN
sequence generator and monitoring
PRI
—Per-link diagnostics and loopbacks
—J1: J1-SF and J1-ESF
■ Programmable system backplane data rates
at 1x/2x/4x/8x of T1/E1 data rates for
■ Programmable transmit/receive slip buffers
support of MVIP, H-MVIP, H.100, and CHI
■ On-chip Intel® Performance Report
Messaging per ANSI T1.231, T1.403, and
ITU G.826
■ Support for fractional T1/E1
■ Signaling:
—Support for T1/E1 CAS and T1/E1 CCS
■ 24 fully independent HDLC controllers
with 128-byte transmit/receive FIFOs
support GR-303 and V5.1/5.2 standards
—Signaling state-change indication
—Signaling freeze/debounce per DS-1
—Signaling force per DS-0
■ FDL Support:
—DL support for ESF per ANSI T1.403 or
■ Red/Yellow/AIS alarm indication
■ Intel®/Motorola* 8-bit processor interface
■ Industry-standard P1149.1 JTAG test port
AT&T* TR54016 (T1/J1)
—DDL bit access for Lucent SLC®96
—Sa bit access for E1
■ Low-power 1.8/3.3-V CMOS technology
■ 256-PBGA package, 17 mm x 17 mm
■ Operating temperature -40 °C to 85 °C
with 5-V tolerant I/Os
Applications
■ Integrated Multi-service Access Platforms ■ Channel service unit (CSU) / Data Service
(IMAPs)
Unit (DSU) equipment
■ Integrated Access Devices (IADs)
■ Wireless base stations, radio network
controllers
■ Routers
■ Inverse Multiplexing for Asynchronous
Transfer Mode (also known as ‘IMA’)
■ Frame-relay access devices
Document Number: 278594
Revision Number: 003
Revision Date: December 2, 2003