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FI1019MTCX

更新时间： 2024-10-27 18:45:51
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 驱动光电二极管接口集成电路驱动器
页数 文件大小 规格书
8页 322K
描述
Line Transceiver, 1 Func, 1 Driver, 1 Rcvr, PDSO14, 4.40 MM, MO-153, TSSOP-14

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中文翻译

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FI1019MTCX 技术参数

生命周期：Obsolete零件包装代码：TSSOP
包装说明：TSSOP,针数：14
Reach Compliance Code：unknownECCN代码：EAR99
HTS代码：8542.39.00.01风险等级：5.84
差分输出：YES驱动器位数：1
输入特性：DIFFERENTIAL接口集成电路类型：LINE TRANSCEIVER
接口标准：EIA-644; TIA-644JESD-30 代码：R-PDSO-G14
长度：5 mm功能数量：1
端子数量：14最高工作温度：85 °C
最低工作温度：-40 °C封装主体材料：PLASTIC/EPOXY
封装代码：TSSOP封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH认证状态：Not Qualified
最大接收延迟：2.5 ns接收器位数：1
座面最大高度：1.2 mm最大供电电压：3.6 V
最小供电电压：3 V标称供电电压：3.3 V
表面贴装：YES温度等级：INDUSTRIAL
端子形式：GULL WING端子节距：0.65 mm
端子位置：DUAL最大传输延迟：1.5 ns
宽度：4.4 mmBase Number Matches：1

FI1019MTCX 数据手册

 浏览型号FI1019MTCX的Datasheet PDF文件第2页浏览型号FI1019MTCX的Datasheet PDF文件第3页浏览型号FI1019MTCX的Datasheet PDF文件第4页浏览型号FI1019MTCX的Datasheet PDF文件第5页浏览型号FI1019MTCX的Datasheet PDF文件第6页浏览型号FI1019MTCX的Datasheet PDF文件第7页 
Preliminary  
November 2000  
Revised December 2000  
FI1019  
3.3V LVDS High Speed Differential Driver/Receiver  
(Preliminary)  
General Description  
Features  
This driver and receiver pair are designed for high speed  
interconnects utilizing Low Voltage Differential Signaling  
(LVDS) technology. The driver translates LVTTL signals to  
LVDS levels with a typical differential output swing of  
350mV and the receiver translates LVDS signals, with a  
typical differential input threshold of 100mV, into LVTTL  
levels. LVDS technology provides low EMI at ultra low  
power dissipation even at high frequencies. This device is  
ideal for high speed clock or data transfer.  
■ Greater than 400Mbs data rate  
■ 3.3V power supply operation  
■ 0.5ns maximum differential pulse skew  
■ 2.5ns maximum propagation delay  
■ Low power dissipation  
■ Power OFF protection  
■ 100mV receiver input sensitivity  
■ Fail safe protection open-circuit, shorted and terminated  
conditions  
■ Meets or exceeds the TIA/EIA-644 LVDS standard  
■ Flow-through pinout simplifies PCB layout  
■ 14-Lead SOIC and TSSOP packages save space  
Ordering Code:  
Order Number Package Number  
Package Description  
FI1019M  
M14A  
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow  
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide  
FI1019MTC  
MTC14  
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.  
Function Table  
Connection Diagram  
Inputs  
Outputs  
RI+  
L
RI−  
H
RE  
L
RO  
L
H
L
L
H
X
X
H
L
Z
Fail Safe Condition  
H
DI  
DE  
DO+  
DO−  
H
L
H
H
L
H
Z
L
Pin Descriptions  
H
L
X
L
Z
H
Pin Name  
Description  
Open−Circuit or Z  
H
DI  
LVTTL Data Input  
H = HIGH Logic Level  
Z = High Impedance  
L = LOW Logic Level  
Fail Safe = Open, Shorted, Terminated  
X = Don’t Care  
DO+  
DO−  
DE  
Non-inverting LVDS Output  
Inverting LVDS Output  
Driver Enable (LVTTL, Active HIGH)  
Non-Inverting LVDS Input  
Inverting LVDS Input  
RI+  
RI−  
RO  
LVTTL Receiver Output  
RE  
VCC  
GND  
Receiver Enable (LVTTL, Active LOW)  
Power Supply  
Ground  
© 2000 Fairchild Semiconductor Corporation  
DS500506  
www.fairchildsemi.com  
12345678

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