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FI1027MX PDF预览

FI1027MX

更新时间: 2024-10-27 20:00:59
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 驱动光电二极管接口集成电路驱动器
页数 文件大小 规格书
4页 66K
描述
Line Driver, 2 Func, 2 Driver, PDSO8, 0.150 INCH, MS-012, SOIC-8

FI1027MX 技术参数

生命周期:Obsolete零件包装代码:SOIC
包装说明:SOP,针数:8
Reach Compliance Code:unknownECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.84
差分输出:YES驱动器位数:2
输入特性:STANDARD接口集成电路类型:LINE DRIVER
接口标准:EIA-644; TIA-644JESD-30 代码:R-PDSO-G8
长度:4.9 mm功能数量:2
端子数量:8最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装形状:RECTANGULAR
封装形式:SMALL OUTLINE认证状态:Not Qualified
最大接收延迟:座面最大高度:1.75 mm
最大供电电压:3.6 V最小供电电压:3 V
标称供电电压:3.3 V表面贴装:YES
温度等级:INDUSTRIAL端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
最大传输延迟:1.5 ns宽度:3.9 mm
Base Number Matches:1

FI1027MX 数据手册

 浏览型号FI1027MX的Datasheet PDF文件第2页浏览型号FI1027MX的Datasheet PDF文件第3页浏览型号FI1027MX的Datasheet PDF文件第4页 
Preliminary  
October 2000  
Revised December 2000  
FI1027  
3.3V LVDS Dual High Speed Differential Driver  
(Preliminary)  
General Description  
Features  
Greater than 600Mbs data rate  
This dual driver is designed for high speed interconnects  
utilizing Low Voltage Differential Signaling (LVDS) technol-  
ogy. The driver translates LVTTL signal levels to LVDS lev-  
els with a typical differential output swing of 350 mV which  
provides low EMI at ultra low power dissipation even at  
high frequencies. This device is ideal for high speed trans-  
fer of clock or data.  
3.3V power supply operation  
0.5ns maximum differential pulse skew  
1.5ns maximum propagation delay  
Low power dissipation  
Power OFF protection  
The FI1027 can be paired with its companion receiver, the  
FI1028, or with any other Fairchild LVDS receiver.  
Meets or exceeds the TIA/EIA-644 LVDS standard  
Flow-through pinout simplifies PCB layout  
8-Lead SOIC package saves space  
Ordering Code:  
Order Number Package Number  
Package Description  
FI1027M  
M08A  
8-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow  
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.  
Pin Descriptions  
Connection Diagram  
Pin Name  
DI1, DI2  
Description  
LVTTL Data Inputs  
Non-inverting Driver Outputs  
Inverting Driver Outputs  
Power Supply  
DO1+, DO2+  
DO1, DO2−  
VCC  
GND  
Ground  
Function Table  
Input  
Outputs  
DI  
L
DO+  
DO−  
H
L
H
L
H
L
OPEN  
H
H = HIGH Logic Level  
L = LOW Logic Level  
X = Don’t Care  
TOP VIEW  
© 2000 Fairchild Semiconductor Corporation  
DS500501  
www.fairchildsemi.com  

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