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FI1031M PDF预览

FI1031M

更新时间: 2024-10-27 19:47:59
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 驱动光电二极管接口集成电路驱动器
页数 文件大小 规格书
6页 194K
描述
Line Driver, 4 Func, 4 Driver, PDSO16, 0.150 INCH, MS-012, SOIC-16

FI1031M 技术参数

生命周期:Obsolete零件包装代码:SOIC
包装说明:SOP,针数:16
Reach Compliance Code:unknownECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.84
差分输出:YES驱动器位数:4
输入特性:STANDARD接口集成电路类型:LINE DRIVER
接口标准:EIA-644; TIA-644JESD-30 代码:R-PDSO-G16
长度:9.9 mm功能数量:4
端子数量:16最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装形状:RECTANGULAR
封装形式:SMALL OUTLINE认证状态:Not Qualified
最大接收延迟:座面最大高度:1.75 mm
最大供电电压:3.6 V最小供电电压:3 V
标称供电电压:3.3 V表面贴装:YES
温度等级:INDUSTRIAL端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
最大传输延迟:2 ns宽度:3.9 mm
Base Number Matches:1

FI1031M 数据手册

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Preliminary  
November 2000  
Revised December 2000  
FI1031  
3.3V LVDS Quad High Speed Differential Driver  
(Preliminary)  
General Description  
Features  
Greater than 400Mbs data rate  
This quad driver is designed for high speed interconnects  
utilizing Low Voltage Differential Signaling (LVDS) technol-  
ogy. The driver translates LVTTL signal levels to LVDS lev-  
els with a typical differential output swing of 350mV which  
provides low EMI at ultra low power dissipation even at  
high frequencies. This device is ideal for high speed trans-  
fer of clock and data.  
3.3V power supply operation  
0.4ns maximum differential pulse skew  
2.0ns maximum propagation delay  
Low power dissipation  
Power OFF protection  
The FI1031 can be paired with its companion receiver, the  
FI1032, or any other Fairchild LVDS receiver.  
100mV receiver input sensitivity  
Meets or exceeds the TIA/EIA-644 LVDS standard  
Pin compatible with equivalent RS-422 and LVPECL  
devices  
16-Lead SOIC and TSSOP packages save space  
Ordering Code:  
Order Number Package Number  
Package Description  
FI1031M  
M16A  
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow  
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide  
FI1031MTC  
MTC16  
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.  
Function Table  
Connection Diagram  
Inputs  
Outputs  
EN  
H
H
H
X
EN  
X
X
X
L
Din  
Dout+  
Dout−  
H
H
L
L
H
L
L
Z
L
H
H
L
L
OPEN  
H
X
L
L
H
H
Z
X
L
OPEN  
X
L
H
H = HIGH Logic Level  
X = Don’t Care  
L = LOW Logic Level  
Z = High Impedance  
Pin Descriptions  
Pin Name  
Din1, Din2, Din3, Din4  
Description  
LVTTL Data Inputs  
Dout1+, Dout2+, Dout3+, Dout4+ Non-Inverting Driver Outputs  
Dout1, Dout2, Dout3, Dout4Inverting Driver Outputs  
EN  
Driver Enable Pin  
EN  
VCC  
GND  
Inverting Driver Enable Pin  
Power Supply  
Ground  
© 2000 Fairchild Semiconductor Corporation  
DS500507  
www.fairchildsemi.com  

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