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FI1032MTCX PDF预览

FI1032MTCX

更新时间: 2024-10-27 14:42:11
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 光电二极管接口集成电路
页数 文件大小 规格书
6页 232K
描述
Line Receiver, 4 Func, 4 Rcvr, PDSO16, 4.40 MM, MO-153, TSSOP-16

FI1032MTCX 技术参数

生命周期:Obsolete零件包装代码:TSSOP
包装说明:TSSOP,针数:16
Reach Compliance Code:unknownECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.84
Is Samacsys:N输入特性:DIFFERENTIAL
接口集成电路类型:LINE RECEIVER接口标准:EIA-644; TIA-644
JESD-30 代码:R-PDSO-G16长度:5 mm
功能数量:4端子数量:16
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:TSSOP
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
认证状态:Not Qualified最大接收延迟:2.5 ns
接收器位数:4座面最大高度:1.2 mm
最大供电电压:3.6 V最小供电电压:3 V
标称供电电压:3.3 V表面贴装:YES
温度等级:INDUSTRIAL端子形式:GULL WING
端子节距:0.65 mm端子位置:DUAL
宽度:4.4 mmBase Number Matches:1

FI1032MTCX 数据手册

 浏览型号FI1032MTCX的Datasheet PDF文件第2页浏览型号FI1032MTCX的Datasheet PDF文件第3页浏览型号FI1032MTCX的Datasheet PDF文件第4页浏览型号FI1032MTCX的Datasheet PDF文件第5页浏览型号FI1032MTCX的Datasheet PDF文件第6页 
Preliminary  
November 2000  
Revised December 2000  
FI1032  
3.3V LVDS Quad High Speed Differential Receiver  
(Preliminary)  
General Description  
Features  
This quad receiver is designed for high speed interconnect  
utilizing Low Voltage Differential Signaling (LVDS) technol-  
ogy. The receiver translates LVDS levels, with a typical dif-  
ferential input threshold of 100mV, to LVTTL signal levels.  
LVDS provides low EMI at ultra low power dissipation even  
at high frequencies. This device is ideal for high speed  
transfer of clock and data.  
Greater than 400Mbs data rate  
3.3V power supply operation  
0.4ns maximum differential pulse skew  
2.5ns maximum propagation delay  
Low power dissipation  
Power OFF protection  
The FI1032 can be paired with its companion driver, the  
FI1031, or any other Fairchild LVDS driver.  
Fail safe protection for open-circuit, shorted and termi-  
nated conditions  
Meets or exceeds the TIA/EIA-644 LVDS standard  
Pin compatible with equivalent RS-422 and LVPECL  
devices  
16-Lead SOIC and TSSOP packages save space  
Ordering Code:  
Order Number Package Number  
Package Description  
FI1032M  
M16A  
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow  
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide  
FI1032MTC  
MTC16  
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.  
Function Table  
Connection Diagram  
Inputs  
Outputs  
EN  
H
H
H
X
EN  
X
X
X
L
Rin+  
H
Rout−  
Rout  
H
L
L
H
L
Fail Safe Condition  
H
H
L
L
H
X
L
H
L
X
L
Fail Safe Condition  
X
H
L
H
Z
H = HIGH Logic Level  
Z = High Impedance  
L = LOW Logic Level  
Fail Safe = Open, Shorted, Terminated  
X = Don’t Care  
Pin Descriptions  
Pin Name  
Description  
Rout1, Rout2, Rout3, Rout4 LVTTL Data Outputs  
Rin1+, Rin2+, Rin3+, Rin4+ Non-Inverting LVDS Inputs  
Rin1, Rin2, Rin3, Rin4Inverting LVDS Inputs  
EN  
Driver Enable Pin  
EN  
VCC  
GND  
Inverting Driver Enable Pin  
Power Supply  
Ground  
© 2000 Fairchild Semiconductor Corporation  
DS500508  
www.fairchildsemi.com  
Print form created on December 11, 2000 10:59  

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