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F49L040A-70N PDF预览

F49L040A-70N

更新时间： 2024-11-24 21:06:11
品牌 Logo 应用领域
晶豪 - ESMT 内存集成电路
页数 文件大小 规格书
41页 313K
描述
Flash, 512KX8, 70ns, PQCC32,

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中文翻译

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F49L040A-70N 技术参数

是否Rohs认证： 不符合生命周期：Contact Manufacturer
包装说明：QCCJ, LDCC32,.5X.6Reach Compliance Code：unknown
风险等级：5.88最长访问时间：70 ns
命令用户界面：YES数据轮询：YES
耐久性：10000 Write/Erase CyclesJESD-30 代码：R-PQCC-J32
JESD-609代码：e0内存密度：4194304 bit
内存集成电路类型：FLASH内存宽度：8
部门数/规模：8端子数量：32
字数：524288 words字数代码：512000
最高工作温度：70 °C最低工作温度：
组织：512KX8封装主体材料：PLASTIC/EPOXY
封装代码：QCCJ封装等效代码：LDCC32,.5X.6
封装形状：RECTANGULAR封装形式：CHIP CARRIER
并行/串行：PARALLEL电源：3.3 V
认证状态：Not Qualified部门规模：64K
最大待机电流：0.0001 A子类别：Flash Memories
最大压摆率：0.03 mA标称供电电压 (Vsup)：3.3 V
表面贴装：YES技术：CMOS
温度等级：COMMERCIAL端子面层：Tin/Lead (Sn/Pb)
端子形式：J BEND端子节距：1.27 mm
端子位置：QUAD切换位：YES
类型：NOR TYPEBase Number Matches：1

F49L040A-70N 数据手册

 浏览型号F49L040A-70N的Datasheet PDF文件第2页浏览型号F49L040A-70N的Datasheet PDF文件第3页浏览型号F49L040A-70N的Datasheet PDF文件第4页浏览型号F49L040A-70N的Datasheet PDF文件第5页浏览型号F49L040A-70N的Datasheet PDF文件第6页浏览型号F49L040A-70N的Datasheet PDF文件第7页 
EFST  
preliminary  
F49L040A  
4 Mbit (512K x 8)  
3V Only CMOS Flash Memory  
1. FEATURES  
!
!
!
Single supply voltage 3.0V-3.6V  
!
!
End of program or erase detection  
- Data polling  
Fast access time: 70/90 ns  
Compatible with JEDEC standard  
- Pin-out, packages and software commands  
compatible with single-power supply Flash  
Low power consumption  
- Toggle bits  
Sector Protection /Un-protection  
- Hardware Protect/Unprotect any combination of sectors  
from a program or erase operation.  
Low VCC Write inhibit is equal to or less than 2.0V  
Boot Sector Architecture  
!
- 7mA typical active current  
!
!
- 25uA typical standby current  
10,000 minimum program/erase cycles  
Command register architecture  
!
!
- U = Upper Boot Sector  
- B = Bottom Boot Sector  
Packages available:  
- Byte programming (9us typical)  
- Sector Erase(sector structure: eight 64 KB)  
Auto Erase (chip & sector) and Auto Program  
- Any combination of sectors can be erased  
concurrently; Chip erase also provided.  
- Automatically program and verify data at specified  
address  
!
- 32-pin TSOPI  
- 32-pin PLCC  
!
!
Erase Suspend/Erase Resume  
- Suspend or Resume erasing sectors to allow the  
read/program in another sector  
2. ORDERING INFORMATION  
Part No  
Boot  
Speed  
Package  
Part No  
Boot  
Speed  
Package  
F49L040A-70T  
F49L040A-70N  
Upper/Bottom  
Upper/Bottom  
70 ns  
70 ns  
TSOPI  
PLCC  
F49L040A-90T  
F49L040A-90N  
Upper/Bottom  
Upper/Bottom  
90 ns  
90 ns  
TSOPI  
PLCC  
3. GENERAL DESCRIPTION  
The F49L040A is a 4 Megabit, 3V only CMOS Flash  
memory device organized as 512K bytes of 8 bits. This  
device is packaged in standard 32-pin TSOPI and 32-pin  
PLCC. It is designed to be programmed and erased both in  
system and can in standard EPROM programmers.  
The F49L040A features a sector erase architecture.  
The device memory array is divided into eight 64 Kbytes.  
Sectors can be erased individually or in groups without  
affecting the data in other sectors. Multiple-sector erase  
and whole chip erase capabilities provide the flexibility to  
revise the data in the device.  
With access times of 70 ns and 90 ns, the F49L040A  
allows the operation of high-speed microprocessors. The  
The sector protect/unprotect feature disables both  
program and erase operations in any combination of the  
sectors of the memory. This can be achieved in-system or  
via programming equipment.  
device has separate chip enable  
, write enable  
,
WE  
CE  
and output enable  
controls. EFST's memory devices  
OE  
reliably store memory data even after 100,000 program  
and erase cycles.  
A low V
CC
detector inhibits write operations on loss of  
power. End of program or erase is detected by the Data  
Polling of DQ7, or by the Toggle Bit I feature on DQ6.  
Once the program or erase cycle has been successfully  
completed, the device internally resets to the Read mode.  
The F49L040A is entirely pin and command set  
compatible with the JEDEC standard for 4 Megabit Flash  
memory devices. Commands are written to the command  
register using standard microprocessor write timings.  
Elite Flash Storage Technology Inc.  
Publication Date : Aug. 2003  
Revision: 0.4  
1/41  
1234567...41

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