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EPM7128AFC100-10 PDF预览

EPM7128AFC100-10

更新时间: 2024-11-02 20:33:19
品牌 Logo 应用领域
阿尔特拉 - ALTERA 时钟LTE输入元件可编程逻辑
页数 文件大小 规格书
60页 876K
描述
EE PLD, 10ns, 128-Cell, CMOS, PBGA100, FINE LINE, BGA-100

EPM7128AFC100-10 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:BGA包装说明:LBGA, BGA100,10X10,40
针数:100Reach Compliance Code:compliant
ECCN代码:3A991HTS代码:8542.39.00.01
风险等级:5.05Is Samacsys:N
其他特性:128 MACROCELLS; 8 LABS; CONFIGURABLE I/O OPERATION WITH 2.5 OR 3.3最大时钟频率:87 MHz
系统内可编程:YESJESD-30 代码:S-PBGA-B100
JESD-609代码:e0JTAG BST:YES
长度:11 mm湿度敏感等级:3
专用输入次数:I/O 线路数量:84
宏单元数:128端子数量:100
最高工作温度:70 °C最低工作温度:
组织:0 DEDICATED INPUTS, 84 I/O输出函数:MACROCELL
封装主体材料:PLASTIC/EPOXY封装代码:LBGA
封装等效代码:BGA100,10X10,40封装形状:SQUARE
封装形式:GRID ARRAY, LOW PROFILE峰值回流温度(摄氏度):245
电源:2.5/3.3,3.3 V可编程逻辑类型:EE PLD
传播延迟:10 ns认证状态:Not Qualified
座面最大高度:1.7 mm子类别:Programmable Logic Devices
最大供电电压:3.6 V最小供电电压:3 V
标称供电电压:3.3 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:BALL
端子节距:1 mm端子位置:BOTTOM
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:11 mm
Base Number Matches:1

EPM7128AFC100-10 数据手册

 浏览型号EPM7128AFC100-10的Datasheet PDF文件第2页浏览型号EPM7128AFC100-10的Datasheet PDF文件第3页浏览型号EPM7128AFC100-10的Datasheet PDF文件第4页浏览型号EPM7128AFC100-10的Datasheet PDF文件第5页浏览型号EPM7128AFC100-10的Datasheet PDF文件第6页浏览型号EPM7128AFC100-10的Datasheet PDF文件第7页 
MAX 7000A  
Programmable Logic  
Device  
Includes  
MAX 7000AE  
®
September 2002, ver. 4.2  
Data Sheet  
High-performance 3.3-V EEPROM-based programmable logic  
devices (PLDs) built on second-generation Multiple Array MatriX  
(MAX®) architecture (see Table 1)  
3.3-V in-system programmability (ISP) through the built-in  
IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface with  
advanced pin-locking capability  
Features...  
MAX 7000AE device in-system programmability (ISP) circuitry  
compliant with IEEE Std. 1532  
EPM7128A and EPM7256A device ISP circuitry compatible with  
IEEE Std. 1532  
Built-in boundary-scan test (BST) circuitry compliant with  
IEEE Std. 1149.1  
Supports JEDEC Jam Standard Test and Programming Language  
(STAPL) JESD-71  
Enhanced ISP features  
Enhanced ISP algorithm for faster programming (excluding  
EPM7128A and EPM7256A devices)  
ISP_Done bit to ensure complete programming (excluding  
EPM7128A and EPM7256A devices)  
Pull-up resistor on I/O pins during in-system programming  
Pin-compatible with the popular 5.0-V MAX 7000S devices  
High-density PLDs ranging from 600 to 10,000 usable gates  
For information on in-system programmable 5.0-V MAX 7000 or 2.5-V  
MAX 7000B devices, see the MAX 7000 Programmable Logic Device Family  
Data Sheet or the MAX 7000B Programmable Logic Device Family Data Sheet.  
f
Table 1. MAX 7000A Device Features  
Feature  
EPM7032AE  
EPM7064AE  
EPM7128AE  
EPM7256AE  
EPM7512AE  
Usable gates  
Macrocells  
600  
32  
2
1,250  
64  
2,500  
128  
8
5,000  
256  
16  
10,000  
512  
Logic array blocks  
4
32  
Maximum user I/O  
pins  
36  
68  
100  
164  
212  
t
PD (ns)  
tSU (ns)  
FSU (ns)  
4.5  
2.9  
4.5  
2.8  
5.0  
3.3  
5.5  
3.9  
7.5  
5.6  
t
2.5  
2.5  
2.5  
2.5  
3.0  
tCO1 (ns)  
3.0  
3.1  
3.4  
3.5  
4.7  
fCNT (MHz)  
227.3  
222.2  
192.3  
172.4  
116.3  
Altera Corporation  
1
DS-M7000A-4.2  

EPM7128AFC100-10 替代型号

型号 品牌 替代类型 描述 数据表
EPM7128AEFC100-5 ALTERA

完全替代

EE PLD, 5ns, 128-Cell, CMOS, PBGA100, FINE LINE, BGA-100
EPM7128AEFC100-7 ALTERA

完全替代

EE PLD, 7.5ns, 128-Cell, CMOS, PBGA100, FINE LINE, BGA-100
EPM7128AEFI100-7 ALTERA

完全替代

EE PLD, 7.5ns, 128-Cell, CMOS, PBGA100, FINE LINE, BGA-100

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