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EPM7064AELI44-7 PDF预览

EPM7064AELI44-7

更新时间: 2024-11-02 20:45:03
品牌 Logo 应用领域
英特尔 - INTEL 时钟输入元件可编程逻辑
页数 文件大小 规格书
66页 1120K
描述
EE PLD, 7.5ns, 64-Cell, CMOS, PQCC44, PLASTIC, LCC-44

EPM7064AELI44-7 技术参数

是否Rohs认证: 不符合生命周期:Active
包装说明:QCCJ, LDCC44,.7SQReach Compliance Code:compliant
ECCN代码:EAR99HTS代码:8542.39.00.01
风险等级:5.11Is Samacsys:N
其他特性:64 MICROCELLS; 4 LABS; CONFIGURABLE I/O OPERATION WITH 2.5 OR 3.3最大时钟频率:135.1 MHz
系统内可编程:YESJESD-30 代码:S-PQCC-J44
JESD-609代码:e0JTAG BST:YES
长度:16.5862 mm湿度敏感等级:1
专用输入次数:I/O 线路数量:36
宏单元数:64端子数量:44
最高工作温度:85 °C最低工作温度:-40 °C
组织:0 DEDICATED INPUTS, 36 I/O输出函数:MACROCELL
封装主体材料:PLASTIC/EPOXY封装代码:QCCJ
封装等效代码:LDCC44,.7SQ封装形状:SQUARE
封装形式:CHIP CARRIER峰值回流温度(摄氏度):220
电源:2.5/3.3,3.3 V可编程逻辑类型:EE PLD
传播延迟:7.5 ns认证状态:Not Qualified
座面最大高度:4.57 mm子类别:Programmable Logic Devices
最大供电电压:3.6 V最小供电电压:3 V
标称供电电压:3.3 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:J BEND
端子节距:1.27 mm端子位置:QUAD
处于峰值回流温度下的最长时间:30宽度:16.5862 mm
Base Number Matches:1

EPM7064AELI44-7 数据手册

 浏览型号EPM7064AELI44-7的Datasheet PDF文件第2页浏览型号EPM7064AELI44-7的Datasheet PDF文件第3页浏览型号EPM7064AELI44-7的Datasheet PDF文件第4页浏览型号EPM7064AELI44-7的Datasheet PDF文件第5页浏览型号EPM7064AELI44-7的Datasheet PDF文件第6页浏览型号EPM7064AELI44-7的Datasheet PDF文件第7页 
MAX 7000A  
Programmable Logic  
Device  
Includes  
MAX 7000AE  
®
October 2002, ver. 4.3  
Data Sheet  
High-performance 3.3-V EEPROM-based programmable logic  
devices (PLDs) built on second-generation Multiple Array MatriX  
(MAX®) architecture (see Table 1)  
3.3-V in-system programmability (ISP) through the built-in  
IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface with  
advanced pin-locking capability  
Features...  
MAX 7000AE device in-system programmability (ISP) circuitry  
compliant with IEEE Std. 1532  
EPM7128A and EPM7256A device ISP circuitry compatible with  
IEEE Std. 1532  
Built-in boundary-scan test (BST) circuitry compliant with  
IEEE Std. 1149.1  
Supports JEDEC Jam Standard Test and Programming Language  
(STAPL) JESD-71  
Enhanced ISP features  
Enhanced ISP algorithm for faster programming (excluding  
EPM7128A and EPM7256A devices)  
ISP_Done bit to ensure complete programming (excluding  
EPM7128A and EPM7256A devices)  
Pull-up resistor on I/O pins during in-system programming  
Pin-compatible with the popular 5.0-V MAX 7000S devices  
High-density PLDs ranging from 600 to 10,000 usable gates  
Extended temperature range  
For information on in-system programmable 5.0-V MAX 7000 or 2.5-V  
MAX 7000B devices, see the MAX 7000 Programmable Logic Device Family  
Data Sheet or the MAX 7000B Programmable Logic Device Family Data Sheet.  
f
Altera Corporation  
1
DS-M7000A-4.3  

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