EDS6416AHBH-TT
DC Characteristics 1 (TA = –20°C to +85°C, VDD, VDDQ = 3.3V ± 0.3V, VSS, VSSQ = 0V)
Parameter
Symbol
Grade
max.
Unit
Test condition
Notes
1, 2, 3
Burst length = 1
tRC = tRC (min.)
Operating current
IDD1
100
mA
CKE = VIL,
tCK = tCK (min.)
Standby current in power down
IDD2P
3
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
6
Standby current in power down
(input signal stable)
IDD2PS
IDD2N
IDD2NS
IDD3P
2
CKE = VIL, tCK = ∞
7
CKE, /CS = VIH,
tCK = tCK (min.)
Standby current in non power down
20
9
4
Standby current in non power down
(input signal stable)
CKE = VIH, tCK = ∞,
/CS = VIH
8
CKE = VIL,
tCK = tCK (min.)
Active standby current in power down
4
1, 2, 6
2, 7
1, 2, 4
2, 8
1, 2, 5
3
Active standby current in power down
(input signal stable)
IDD3PS
3
CKE = VIL, tCK = ∞
CKE, /CS = VIH,
tCK = tCK (min.)
Active standby current in non power down IDD3N
35
20
120
220
1.5
Active standby current in non power down
IDD3NS
CKE = VIH, tCK = ∞,
/CS = VIH
(input signal stable)
tCK = tCK (min.),
BL = 4
Burst operating current
Refresh current
IDD4
IDD5
IDD6
tRC = tRC (min.)
VIH ≥ VDD – 0.2V
VIL ≤ 0.2V
Self refresh current
Notes: 1. IDD depends on output load condition when the device is selected. IDD (max.) is specified at the output
open condition.
2. One bank operation.
3. Input signals are changed once per one clock.
4. Input signals are changed once per two clocks.
5. Input signals are changed once per four clocks.
6. After power down mode, CLK operating current.
7. After power down mode, no CLK operating current.
8. Input signals are VIH or VIL fixed.
Data Sheet E0718E20 (Ver. 2.0)
5