Datasheet > EDS6416AHTA-TI

EDS6416AHTA-TI

更新时间： 2022-11-25 11:01:34

品牌	Logo	应用领域
尔必达 - ELPIDA		动态存储器
页数	文件大小	规格书
49页	676K
描述
64M bits SDRAM WTR (Wide Temperature Range)

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EDS6416AHTA-TI 数据手册

PRELIMINARY DATA SHEET

64M bits SDRAM

WTR (Wide Temperature Range)

EDS6416AHTA-TI (4M words × 16 bits)

Description

Pin Configurations

The EDS6416AHTA is a 64M bits SDRAMs organized

as 1,048,576 words × 16 bits × 4 banks. All inputs and

outputs are synchronized with the positive edge of the

clock.

/xxx indicate active low signal.

54-pin Plastic TSOP (II)

VDD

DQ0

VDDQ

DQ1

DQ2

VSSQ

DQ3

DQ4

VDDQ

DQ5

DQ6

VSSQ

DQ7

VDD

LDQM

/WE

/CAS

/RAS

/CS

BA0

BA1

A10

VDD

VSS

DQ15

VSSQ

DQ14

DQ13

VDDQ

DQ12

DQ11

VSSQ

DQ10

DQ9

VDDQ

DQ8

VSS

UDQM

CLK

CKE

A11

It is packaged in 54-pin plastic TSOP (II).

Features

• 3.3V power supply

• Clock frequency: 133MHz (max.)

• Single pulsed /RAS

• ×16 organization

• 4 banks can operate simultaneously and

independently

• Burst read/write operation and burst read/single

write operation capability

• 2 variations of burst sequence

Sequential (BL = 1, 2, 4, 8, full page)

Interleave (BL = 1, 2, 4, 8)

• Programmable /CAS latency (CL): 2, 3

• Byte control by UDQM and LDQM

• Refresh cycles: 4096 refresh cycles/64ms

• 2 variations of refresh

VSS

Auto refresh

Self refresh

(Top view)

• TSOP (II) package with lead free solder (Sn-Bi)

• Wide temperature range

Ambient temperature range: –40 to +85°C

A0 to A11

Address input

BA0, BA1

DQ0 to DQ15

/CS

Bank select address

Data-input/output

Chip select

/RAS

/CAS

/WE

Row address strobe

Column address strobe

Write enable

LDQM, UDQM

CKE

Input/output mask

Clock enable

CLK

Clock input

VDD

VSS

VDDQ

VSSQ

Power for internal circuit

Ground for internal circuit

Power for DQ circuit

Ground for DQ circuit

No connection

Document No. E0636E10 (Ver. 1.0)

Date Published January 2005 (K) Japan

Printed in Japan

URL: http://www.elpida.com

Elpida Memory, Inc. 2005

12 3 4 5 6 7...49

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