Datasheet > 存储 > SRAM> EDI8L32128V20AI

EDI8L32128V20AI

更新时间： 2024-11-16 03:12:39

品牌	Logo	应用领域
WEDC		存储内存集成电路静态存储器
页数	文件大小	规格书
7页	190K
描述
128Kx32 CMOS High Speed Static RAM

阅读下载

中文翻译

获取价格

数据手册

如果您发现信息不准确，欢迎纠错

EDI8L32128V20AI 数据手册

EDI8L32128V

White Electronic Designs

128Kx32 CMOS High Speed Static RAM

FEATURES

DESCRIPTION

The EDI8L32128V is a high speed, 3.3V, four megabit

density Static RAM. The device is available with access

times of 12, 15 and 20ns, allowing the device to support

60MH_ZDSPs with no wait states. The high speed, 3.3V

supply voltage and byte conﬁgurability make the device

ideal for interfacing with Analog Devices ADSP-21062L or

ADSP-21060L SHARC DSPs.

ꢀ

128Kx32 bit CMOS Static

Analog SHARC^TMExternal Memory Solution

ꢀ

ADSP-21060L

ADSP-21062L

ꢀ

Random Access Memory Array

ꢀ

Fast Access Times: 12, 15 and 20ns

User Conﬁgurable Organization

with Minimal Additional Logic

The device can be conﬁgured as a 128Kx32 and used to

create a single chip external data memory solution for the

SHARC (ﬁgure 1). Providing a 51ꢀ space savings when

compared to four 128Kx8, 400mil wide plastic SOJs. The

EDI8L32128V has a 10pf load on the data lines vs. 24pf for

four plastic SOJs. Memory upgrades in the same footprint

can be accomplished with the EDI8L32256V (256Kx32) or

the EDI8L32512V (512KX32). This is covered in detail in

the application report "The EDI's x32 MCM-L SRAM Family:

Integrated Memory Solution for the Analog SHARC DSP"

Master Output Enable and Write Control

TTL Compatible Inputs and Outputs

Fully Static, No Clocks

ꢀ

Surface Mount Package

ꢀ

68 Lead PLCC, No. 99 (JEDEC MO-47AE)

Small Footprint, 0.990 Sq. In.

Multiple Ground Pins for Maximum

Noise Immunity

Alternatively the device's chip enables can conﬁgure it as a

256Kx16. A256Kx48 program memory array for the SHARC

is created using three devices (ﬁgure 2). If this memory is

too deep, two 128Kx24's (EDI8L24128V) can be used to

create a 128Kx48 memory array.

Single 3.3V ( 5ꢀ) Supply Operation

Note: Solder Reﬂow temperature should not exceed 26ꢀ°C for 1ꢀ seconds

PIN CONFIGURATIONS AND

BLOCK DIAGRAM

PIN NAMES

AØ-A16

EØ#-E3#

Address Inputs

Chip Enables (One per Byte)

Master Write Enable

Master Output Enable

Common Data Input/Output

Power (+3.3V 1ꢀ0)

Ground

60 DQ14

DQØ-DQ31

V_CC

V_SS

DQ17 10

DQ18 11

DQ19 12

59 DQ13

58 DQ12

^SS13

56 DQ11

55 DQ10

54 DQ9

53 DQ8

DQ20 14

DQ21 15

DQ22 16

DQ23 17

No Connection

^CC18

51 DQ7

50 DQ6

49 DQ5

48 DQ4

DQ24 19

DQ25 20

DQ26 21

DQ27 22

A0-A16

^SS23

46 DQ3

45 DQ2

44 DQ1

DQ28 24

DQ29 25

DQ30 26

E0#

E1#

E2#

E3#

DQ0-DQ7

128Kx32

Memory

Array

DQ8-DQ15

DQ16-DQ23

DQ24-DQ31

Note: Pin 2 & 67 on the 64Kx32 (EDI8L3265C) and the 256Kx32 (EDI8L32256C) are

word select pins.

White Electronic Designs Corp. reserves the right to change products or speciﬁcations without notice.

July 2004

Rev. 6

White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

12 3 4 5 6 7

中文翻译

下载PDF

与EDI8L32128V20AI相关器件

型号	品牌	获取价格	描述	数据表
EDI8L32128V-AC	ETC	获取价格	TMS320C3000. TMS320C4000 Families
EDI8L32256B12AC	ETC	获取价格	x32 SRAM
EDI8L32256B15AC	ETC	获取价格	x32 SRAM
EDI8L32256B15AI	ETC	获取价格	x32 SRAM
EDI8L32256C	ETC	获取价格	256Kx32, 5V Static Ram
EDI8L32256C10AC	WEDC	获取价格	SRAM Module, 256KX32, 10ns, CMOS, PQCC68, 0.990 X 0.990 INCH, PLASTIC, LCC-68
EDI8L32256C12AC	WEDC	获取价格	SRAM Module, 256KX32, 12ns, CMOS, PQCC68, 0.990 X 0.990 INCH, PLASTIC, LCC-68
EDI8L32256C15AC	ETC	获取价格	256Kx32, 5V Static Ram
EDI8L32256C17AC	ETC	获取价格	256Kx32, 5V Static Ram
EDI8L32256C17AI	ETC	获取价格	256Kx32, 5V Static Ram

与EDI8L32128V20AI相关文章

解析光耦仿真器：升级光耦合器技术的必要性
2024-11-18

14
英伟达新一代Blackwell GPU过热问题致交付延迟
2024-11-18

7
国产厂商思特威CMOS图像传感器芯片单月出货超1亿颗，技术创新引领行业发展
2024-11-14

36
台积电5nm和3nm产能利用率达100%，半导体行业景气度持续攀升
2024-11-14

31

产品中心

服务支持

精选活动

关于我们

帮助中心

EDI8L32128V20AI

EDI8L32128V20AI 数据手册

与EDI8L32128V20AI相关器件

与EDI8L32128V20AI相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

EDI8L32128V20AI

EDI8L32128V20AI 数据手册

与EDI8L32128V20AI相关器件

与EDI8L32128V20AI相关文章

您还可以找

您在本页遇到什么问题？