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EDI8L32256C25AI PDF预览

EDI8L32256C25AI

更新时间: 2024-11-16 06:55:55
品牌 Logo 应用领域
其他 - ETC 内存集成电路静态存储器
页数 文件大小 规格书
5页 64K
描述
256Kx32, 5V Static Ram

EDI8L32256C25AI 数据手册

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EDI8L32256C  
256Kx32 SRAM Module  
256Kx32, 5V Static Ram  
Features  
The EDI8L32256C is a high speed, 5V, 8 megabit SRAM.  
The device is available with access times of 15, 17, 20 and  
25ns, allowing the creation of a no wait state DSP memory  
solution.  
The device can be configured as a 256Kx32 and used to  
create a single chip external data memory solution for  
Texas Instruments' TMS320C30/31, TMS 320C32 or  
TMS320C4x, Motorola's DSP96002 and Analog Device's  
SHARCTM DSP.  
256Kx32 bit CMOS Static  
DSP Memory Solution  
Texas Instruments TMS320C3x, TMS320C4x  
Analog SHARCTM DSP  
Motorola DSP96002  
Random Access Memory Array  
• Fast Access Times: 15, 17, 20 and 25ns  
Individual Byte Enables  
Alternatively the device's chip enables can be used to  
configure it as a 512Kx16. A 512Kx48 program memory  
array for Analog's SHARCTM DSP is created using three  
devices. If this memory is too deep, two 256Kx24s  
(EDI8L24256C) can be used to create a 256Kx48 array or  
two 128Kx24s (EDI8L24128C) can be used to create a  
128Kx48 array.  
The device provides a 32% space savings when compared  
to two monolithic 256Kx16, 44 pin SOJs.  
The device provides a memory upgrade of the  
EDI8L32128C (128Kx32) and the EDI8L3265C (64Kx32).  
For more memory the device can be upgraded to the  
EDI8L32512C (512Kx32).  
User Configurable Organization  
with Minimal Additional Logic  
Master Output Enable and Write Control  
TTL Compatible Inputs and Outputs  
• Fully Static, No Clocks  
Surface Mount Package  
• 68 Lead PLCC, No. 99, JEDEC MO-47AE  
• Small Footprint, 0.990 Sq. In.  
Multiple Ground Pins for Maximum  
Noise Immunity  
Single +5V (±5%) Supply Operation  
NOTE: Solder Reflow temperature should not exceed 260°C for 10 seconds.  
Pin Configurations and Block Diagram  
Pin Names  
AØ-A17  
EØ-E1  
BSØ-BS3  
W
Address Inputs  
Chip Enables (One per Word)  
Byte Selects (One per Byte)  
Master Write Enable  
Master Output Enable  
Common Data Input/Output  
Power(+5V±5%)  
60 DQ14  
DQ17 10  
59 DQ13  
DQ18 11  
58 DQ12  
DQ19 12  
57 VSS  
VSS 13  
G
56 DQ11  
DQ20 14  
55 DQ10  
DQ21 15  
54 DQ9  
DQ22 16  
53 DQ8  
DQ23 17  
52 VCC  
VCC 18  
DQØ-DQ31  
VCC  
VSS  
NC  
Ground  
No Connection  
51 DQ7  
DQ24 19  
50 DQ6  
DQ25 20  
49 DQ5  
DQ26 21  
48 DQ4  
DQ27 22  
47 VSS  
VSS 23  
46 DQ3  
DQ28 24  
45 DQ2  
DQ29 25  
44 DQ1  
DQ30 26  
AØ-A17  
G
18  
W
EØ  
E1  
BSØ  
BS1  
BS2  
BS3  
256Kx32  
Memory  
DQØ-DQ7  
Array  
DQ8-DQ15  
DQ16-DQ23  
DQ24-DQ31  
Note: For memory upgrade information refer to page 8, Figure 8 "EDI MCM-L  
upgradepath".  
Electronic Designs Incorporated  
• One Research Drive • Westborough, MA 01581USA • 508-366-5151 • FAX 508-836-4850 •  
http://www.electronic-designs.com  
1
EDI8L32256C Rev. 4 3/98 ECO#9662  

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