n 256Kx32 bit CMOS Static
The EDI8L32256V is a high speed, 3.3 volt, 8 megabit SRAM.
The device is available with access times of 12, 15, 17 and
20ns, allowing the creation of a no wait state DSP memory
solution.
n DSP Memory Solution
• ADSP - 21060L (SHARC)
• ADSP - 21062L (SHARC)
The device can be configured as a 256Kx32 and used to
create a single chip external data memory solution for Texas
Instruments' TMS320LC31 (figure 3), or Analog Device's
SHARCTM DSP (figure 4).
• TMS320LC31
n Random Access Memory Array
• Fast Access Times: 12, 15, 17 and 20ns
• Individual Byte Enables
Alternatively the device's chip enables can be used to con-
figure it as a 512Kx16. A 512Kx48 program memory array
for Analog's SHARC DSP is created using three devices (fig-
ure 5). If this memory is too deep, two 256Kx24s
(EDI8L24256V) can be used to create a 256Kx48 array or
two 128Kx24s (EDI8L24128V) can be used to create a
128Kx48 array.
• User Configurable Organization
with Minimal Additional Logic
• Master Output Enable and Write Control
• TTL Compatible Inputs and Outputs
• Fully Static, No Clocks
The device provides a 32ꢀ space savings when compared
to two monolithic 256Kx16, 44 pin SOJs.
n Surface Mount Package
The device provides a memory upgrade of the EDI8L32128V
(128Kx32). For more memory the device can be upgraded
to the EDI8L32512V (512Kx32). For additional upgrade in-
formation see figure 6.
• 68 Lead PLCC, No. 99 JEDEC MO-47AE
• Small Footprint, 0.990 Sq. In.
• Multiple Ground Pins for Maximum Noise Immunity
n Single 3.3V ( 5ꢀ) Supply Operation
NOTE: Solder Reflow temperature should not exceed 260°C for 10 seconds.
AØ-A17
EØ-E1
BSØ-BS3
W
Address Inputs
Chip Enables (One per Word)
Byte Selects (One per Byte)
Master Write Enable
Master Output Enable
Common Data Input/Output
Power (3*3V±5%)
G
DQØ-DQ31
VCC
VSS
Ground
NC
No Connection
March, 1998 Rev. 2
ECO# 10135
White Electronic Designs Corporation • Westborough, MA 01581 •
(508) 366-5151 www.whiteedc.com