Datasheet > EDI8F32512V17AI

EDI8F32512V17AI

更新时间： 2023-01-02 21:05:29

品牌	Logo	应用领域
WEDC		静态存储器
页数	文件大小	规格书
8页	112K
描述
SRAM Module, 512KX32, 17ns, CMOS, PQCC68, PLASTIC, MO-47AE, LCC-68

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中文翻译

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数据手册

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EDI8F32512V17AI 数据手册

EDI8F32512V

White Electronic

512Kx32 SRAM Module.3.3V

FEATURES

DESCRIPTION

ꢀ

DSP Memory Solution

The EDI8F32512V is a high speed, 3.3V, 16 megabit SRAM.

The device is available with access times of 12, 15, 17 and

20ns allowing the creation of a no wait state DSP and RISC

microprocessor memory solutions.

ꢀ

ADSP-21060L (SHARC)

ADSP-21062L (SHARC)

Texas Instruments TMS320LC31

The device can be conﬁgured as a 512K x 32 and used to

create a single chip external data memory solution for TI's

TMS320LC31 (ﬁgure 5), or Analog's SHARC^TMDSP (ﬁgure

6).

ꢀ

RISC Memory Solution

MPC860 (Power Quic)

Random Access Memory Array

ꢀ

The device provides a 56% space savings when compared

to four 512Kx8, 36 pin SOJs. In addition the EDI8K32512V

has only a 10pF load on the data lines vs. 32 pF for four

plastic SOJs.

ꢀ

Fast Access Times: 12, 15, 17, and 20ns

Individual Byte Enables

User conﬁguration organization with Minimal

Additional Logic

The device provides a memory upgrade of the EDI8F32256V

(256K x 32) or the EDI8L32128V (128K x 32) (ﬁgure 8).

Alternatively, the device's chip enables can conﬁgure it as

a 1M x 16. A 1M x 48 program memory array for Analog's

CHARC DSP is created using three devices (ﬁgure 7). If

this memory is too deep, two 512K x 24s (EDI8L24512V)

can be used to create a 512K x 48 array or two 128K x

24s (EDI8L24128V) can be used to create a 128K x 48

array.

ꢀ

Master Output Enable and Write Control

TTL Compatible Inputs and Outputs

Fully Static, No Clocks

ꢀ

Surface Mount Package

ꢀ

68 Lead PLCC, No. 99 JEDEC MO-47AE

Small Footprint, 0.990 Sq. In.

Multiple Ground Pins for Maximum Noise

Immunity

Note: Soldier Reﬂow Temperature should not exceed 260°C for 10 seconds.

Single +3.3V (±5%) Supply Operation

FIG. 1

PIN DESCRIPTION

A0-A18

Address Inputs

PIN CONFIGURATIONS

E0#-E3#

Chip Enables

(One per Byte)

Master Write Enable

Master Output Enable

60 DQ14

59 DQ13

58 DQ12

DQ17 10

DQ18 11

DQ19 12

DQ0-DQ31

Common Data

Input/Output

VSS

V_CC

V_SS

Power (+3.3V±5%)

Ground

56 DQ11

55 DQ10

54 DQ9

53 DQ8

52 V^CC

51 DQ7

50 DQ6

49 DQ5

48 DQ4

DQ20 14

DQ21 15

DQ22 16

DQ23 17

No Connectiona

DQ24 19

DQ25 20

DQ26 21

DQ27 22

BLOCK DIAGRAM

A0-18

VSS

46 DQ3

45 DQ2

44 DQ1

DQ28 24

DQ29 25

DQ30 26

DQ0-DQ7

512K x 32

Memory

Array

E0#

E1#

E2#

E3#

DQ8-DQ15

DQ16-DQ23

DQ24-DQ31

White Electronic Designs Corp. reserves the right to change products or speciﬁcations without notice.

October. 2000

Rev. 3

White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com

12 3 4 5 6 7 8

中文翻译

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与EDI8F32512V17AI相关器件

型号	品牌	获取价格	描述	数据表
EDI8F32512V20MMC	WEDC	获取价格	512Kx32 Static RAM CMOS, High Speed Module
EDI8F32512V20MZC	WEDC	获取价格	512Kx32 Static RAM CMOS, High Speed Module
EDI8F32512V25MMC	WEDC	获取价格	512Kx32 Static RAM CMOS, High Speed Module
EDI8F32512V25MZC	WEDC	获取价格	512Kx32 Static RAM CMOS, High Speed Module
EDI8F32512V-MM	ETC	获取价格	SRAM Modules
EDI8F3264C20M6C	ETC	获取价格	x32 SRAM Module
EDI8F3264C25M6C	ETC	获取价格	x32 SRAM Module
EDI8F3264C35M6C	ETC	获取价格	x32 SRAM Module
EDI8F3265C12MNC	WEDC	获取价格	SRAM Module, 64KX32, 12ns, CMOS, ANGLED, SIMM-64
EDI8F3265C12MZI	WEDC	获取价格	SRAM Module, 64KX32, 12ns, CMOS, ZIP-64

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