Datasheet > EDI88130LPS25L32C

EDI88130LPS25L32C

更新时间： 2024-11-03 05:19:15

品牌	Logo	应用领域
美高森美 - MICROSEMI		静态存储器
页数	文件大小	规格书
9页	255K
描述
Standard SRAM, 128KX8, 25ns, CMOS, CQCC32, CERAMIC, LCC-32

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EDI88130CS

HI-RELIABILITY PRODUCT

128Kx8 Monolithic SRAM, SMD 5962-89598

FEATURES

The EDI88130CS is a high speed, high performance, 128Kx8 bits

monolithic Static RAM.

■ Access Times of 15*, 17, 20, 25, 35, 45, 55ns

■ Battery Back-up Operation

• 2V Data Retention (EDI88130LPS)

An additional chip enable line provides system memory security

during power down in non-battery backed up systems and memory

banking in high speed battery backed systems where large mul-

tiple pages of memory are required.

■ CS¹, CS2 & OE Functions for Bus Control

■ Inputs and Outputs Directly TTL Compatible

■ Organized as 128Kx8

The EDI88130CS has eight bi-directional input-output lines to

provide simultaneous access to all bits in a word.

■ Commercial, Industrial and Military Temperature Ranges

■ Thru-hole and Surface Mount Packages JEDEC Pinout

A low power version, EDI88130LPS, offers a 2V data retention

function for battery back-up applications.

• 32 pin Sidebrazed Ceramic DIP, 400 mil (Package 102)

• 32 pin Sidebrazed Ceramic DIP, 600 mil (Package 9)

• 32 lead Ceramic SOJ (Package 140)

Military product is available compliant to MIL-PRF-38535.

15ns access time is advanced information, contact factory for availability.

• 32 pad Ceramic Quad LCC (Package 12)

• 32 pad Ceramic LCC (Package 141)

• 32 lead Ceramic Flatpack (Package 142)

■ Single +5V (±10%) Supply Operation

FIG. 1 PIN CONFIGURATION

32 DIP

32 SOJ

32 CLCC

32 FLATPACK

PIN DESCRIPTION

32 QUAD LCC

TOP VIEW

I/O0-7

A0-16

Data Inputs/Outputs

Address Inputs

Write Enable

TOP VIEW

31 30

A16

A14

A12

A2 10

A1 11

AØ 12

I/OØ 13

I/O1 14

I/O2 15

32 VCC

CS1, CS2

Chip Selects

31 A15

30 CS2

29 WE

28 A13

27 A8

Output Enable

Power (+5V ±10%)

Ground

VCC

VSS

26 A9

Not Connected

25 A11

24 OE

23 A10

22 CS1

21 I/O7

20 I/O6

19 I/O5

18 I/O4

17 I/O3

I/O

BLOCK DIAGRAM

I/O

Memory Array

17 18

SS 16

Address

Buffer

Address

Decoder

I/O

Circuits

Ø-16

I/OØ-7

CS2

February 2000 Rev. 9

White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com

12 3 4 5 6 7...9

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与EDI88130LPS25L32C相关器件

型号	品牌	获取价格	描述	数据表
EDI88130LPS25L32I	MICROSEMI	获取价格	Standard SRAM, 128KX8, 25ns, CMOS, CQCC32, CERAMIC, LCC-32
EDI88130LPS25L32M	MICROSEMI	获取价格	Standard SRAM, 128KX8, 25ns, CMOS, CQCC32, CERAMIC, LCC-32
EDI88130LPS25LB	MICROSEMI	获取价格	Standard SRAM, 128KX8, 25ns, CMOS, CDSO32,
EDI88130LPS25LC	MICROSEMI	获取价格	Standard SRAM, 128KX8, 25ns, CMOS, CDSO32, CERAMIC, LCC-32
EDI88130LPS25LM	MICROSEMI	获取价格	Standard SRAM, 128KX8, 25ns, CMOS, CDSO32, CERAMIC, LCC-32
EDI88130LPS25NB	MICROSEMI	获取价格	Standard SRAM, 128KX8, 25ns, CMOS, CDSO32, CERAMIC, SOJ-32
EDI88130LPS25NC	MICROSEMI	获取价格	Standard SRAM, 128KX8, 25ns, CMOS, CDSO32, CERAMIC, SOJ-32
EDI88130LPS25NI	MICROSEMI	获取价格	Standard SRAM, 128KX8, 25ns, CMOS, CDSO32, CERAMIC, SOJ-32
EDI88130LPS25NM	MICROSEMI	获取价格	Standard SRAM, 128KX8, 25ns, CMOS, CDSO32, CERAMIC, SOJ-32
EDI88130LPS25TC	MICROSEMI	获取价格	Standard SRAM, 128KX8, 25ns, CMOS, CDIP32, 0.400 INCH, SIDE BRAZED, CERAMIC, DIP-32

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