Datasheet > EDI88130LPS25LC

EDI88130LPS25LC

更新时间： 2024-11-03 04:22:35

品牌	Logo	应用领域
美高森美 - MICROSEMI		静态存储器
页数	文件大小	规格书
10页	1086K
描述
Standard SRAM, 128KX8, 25ns, CMOS, CDSO32, CERAMIC, LCC-32

阅读下载

中文翻译

获取价格

数据手册

如果您发现信息不准确，欢迎纠错

EDI88130LPS25LC 数据手册

EDI88130CS

128Kx8 Monolithic SRAM, SMD 5962-89598

FEATURES

 Access Times of 15*, 17, 20, 25, 35, 45, 55ns

An additional chip enable line provides system memory security

during power down in non-battery backed up systems and memory

banking in high speed battery backed systems where large multiple

pages of memory are required.

 Battery Back-up Operation

• 2V Data Retention (EDI88130LPS)

 CS1#, CS2 & OE# Functions for Bus Control

 Inputs and Outputs Directly TTL Compatible

 Organized as 128Kx8

The EDI88130CS has eight bi-directional input-output lines to provide

simultaneous access to all bits in a word.

A low power version, EDI88130LPS, offers a 2V data retention

function for battery back-up applications.

 Commercial, Industrial and Military Temperature Ranges

 Thru-hole and Surface Mount Packages JEDEC Pinout

• 32 pin Sidebrazed Ceramic DIP, 400 mil (Package 102)

• 32 pin Sidebrazed Ceramic DIP, 600 mil (Package 9)

• 32 lead Ceramic SOJ (Package 140)

Military product is available compliant to MIL-PRF-38535.

* 15ns access time is advanced information, contact factory for availability.

This product is subject to change without notice.

• 32 pad Ceramic Quad LCC (Package 12)

• 32 pad Ceramic LCC (Package 141)

• 32 lead Ceramic Flatpack (Package 142)

 Single +5V (±10%) Supply OperationThe EDI88130CS is

a high speed, high performance, 128Kx8 bits monolithic

Static RAM.

FIGURE 1 – PIN CONFIGURATION

32 DIP

32 SOJ

32 QUAD LCC

TOP VIEW

PIN DESCRIPTION

32 CLCC

I/O0-7

A0-16

WE#

Data Input/Output

Address Inputs

Write Enable

Chip Select

32 FLATPACK

CS1#, CS2

OE#

TOP VIEW

31 30

Output Enable

Power Supply

Ground

I/O0

WE#

A13

V_CC

A16

A14

A12

32 V_CC

31 A15

30 CS2#

29 WE#

28 A13

27 A8

V_SS

Not Connected

A11

OE#

A10

CS1#

I/O7

26 A9

25 A11

24 OE#

23 A10

22 CS1#

21 I/O7

20 I/O6

19 I/O5

18 I/O4

17 I/O3

Block Diagram

A2 10

A1 11

Memory Array

17 18

A0 12

I/O0 13

I/O1 14

I/O2 15

V_SS16

Address

Buffer

Address

Decoder

I/O

Circuits

A0-16

I/O0-7

WE#

CS1#

CS2

OE#

Microsemi Corporation reserves the right to change products or speciﬁcations without notice.

Rev. 13

Microsemi Corporation • (602) 437-1520 • www.microsemi.com

12 3 4 5 6 7...10

中文翻译

下载PDF

与EDI88130LPS25LC相关器件

型号	品牌	获取价格	描述	数据表
EDI88130LPS25LM	MICROSEMI	获取价格	Standard SRAM, 128KX8, 25ns, CMOS, CDSO32, CERAMIC, LCC-32
EDI88130LPS25NB	MICROSEMI	获取价格	Standard SRAM, 128KX8, 25ns, CMOS, CDSO32, CERAMIC, SOJ-32
EDI88130LPS25NC	MICROSEMI	获取价格	Standard SRAM, 128KX8, 25ns, CMOS, CDSO32, CERAMIC, SOJ-32
EDI88130LPS25NI	MICROSEMI	获取价格	Standard SRAM, 128KX8, 25ns, CMOS, CDSO32, CERAMIC, SOJ-32
EDI88130LPS25NM	MICROSEMI	获取价格	Standard SRAM, 128KX8, 25ns, CMOS, CDSO32, CERAMIC, SOJ-32
EDI88130LPS25TC	MICROSEMI	获取价格	Standard SRAM, 128KX8, 25ns, CMOS, CDIP32, 0.400 INCH, SIDE BRAZED, CERAMIC, DIP-32
EDI88130LPS25TI	MICROSEMI	获取价格	Standard SRAM, 128KX8, 25ns, CMOS, CDIP32, 0.400 INCH, SIDE BRAZED, CERAMIC, DIP-32
EDI88130LPS25TM	MICROSEMI	获取价格	Standard SRAM, 128KX8, 25ns, CMOS, CDIP32, 0.400 INCH, SIDE BRAZED, CERAMIC, DIP-32
EDI88130LPS35CB	MICROSEMI	获取价格	Standard SRAM, 128KX8, 35ns, CMOS, CDIP32, 0.600 INCH, SIDE BRAZED, CERAMIC, DIP-32
EDI88130LPS35CC	MICROSEMI	获取价格	Standard SRAM, 128KX8, 35ns, CMOS, CDIP32, 0.600 INCH, SIDE BRAZED, CERAMIC, DIP-32

与EDI88130LPS25LC相关文章

英伟达新AI芯片Rubin或提前半年亮相
2024-11-05

4
苹果iPhone 17将全系采用三星/LG显示LTPO OLED面板
2024-11-05

2
三星深化印度制造布局，供应链本地化进程加速
2024-10-29

23
芯擎科技“星辰一号”自动驾驶芯片点亮成功，2025年量产在即
2024-10-29

24

产品中心

服务支持

精选活动

关于我们

帮助中心

EDI88130LPS25LC

EDI88130LPS25LC 数据手册

与EDI88130LPS25LC相关器件

与EDI88130LPS25LC相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

EDI88130LPS25LC

EDI88130LPS25LC 数据手册

与EDI88130LPS25LC相关器件

与EDI88130LPS25LC相关文章

您还可以找

您在本页遇到什么问题？