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EDI88130LPS17LM PDF预览

EDI88130LPS17LM

更新时间: 2024-11-01 14:51:11
品牌 Logo 应用领域
美高森美 - MICROSEMI 静态存储器内存集成电路
页数 文件大小 规格书
9页 255K
描述
Standard SRAM, 128KX8, 17ns, CMOS, CDSO32

EDI88130LPS17LM 技术参数

是否Rohs认证:不符合生命周期:Active
零件包装代码:DLCC包装说明:SON, SOLCC32,.4
针数:32Reach Compliance Code:unknown
风险等级:5.66Is Samacsys:N
最长访问时间:17 nsI/O 类型:COMMON
JESD-30 代码:R-XDSO-N32内存密度:1048576 bit
内存集成电路类型:STANDARD SRAM内存宽度:8
端子数量:32字数:131072 words
字数代码:128000工作模式:ASYNCHRONOUS
最高工作温度:125 °C最低工作温度:-55 °C
组织:128KX8输出特性:3-STATE
封装主体材料:CERAMIC封装代码:SON
封装等效代码:SOLCC32,.4封装形状:RECTANGULAR
封装形式:SMALL OUTLINE并行/串行:PARALLEL
电源:5 V认证状态:Not Qualified
最大待机电流:0.002 A最小待机电流:2 V
子类别:SRAMs最大压摆率:0.3 mA
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS温度等级:MILITARY
端子形式:NO LEAD端子节距:1.27 mm
端子位置:DUALBase Number Matches:1

EDI88130LPS17LM 数据手册

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EDI88130CS  
HI-RELIABILITY PRODUCT  
128Kx8 Monolithic SRAM, SMD 5962-89598  
FEATURES  
The EDI88130CS is a high speed, high performance, 128Kx8 bits  
monolithic Static RAM.  
Access Times of 15*, 17, 20, 25, 35, 45, 55ns  
Battery Back-up Operation  
• 2V Data Retention (EDI88130LPS)  
An additional chip enable line provides system memory security  
during power down in non-battery backed up systems and memory  
banking in high speed battery backed systems where large mul-  
tiple pages of memory are required.  
CS1, CS2 & OE Functions for Bus Control  
Inputs and Outputs Directly TTL Compatible  
Organized as 128Kx8  
The EDI88130CS has eight bi-directional input-output lines to  
provide simultaneous access to all bits in a word.  
Commercial, Industrial and Military Temperature Ranges  
Thru-hole and Surface Mount Packages JEDEC Pinout  
A low power version, EDI88130LPS, offers a 2V data retention  
function for battery back-up applications.  
• 32 pin Sidebrazed Ceramic DIP, 400 mil (Package 102)  
• 32 pin Sidebrazed Ceramic DIP, 600 mil (Package 9)  
• 32 lead Ceramic SOJ (Package 140)  
Military product is available compliant to MIL-PRF-38535.  
*
15ns access time is advanced information, contact factory for availability.  
• 32 pad Ceramic Quad LCC (Package 12)  
• 32 pad Ceramic LCC (Package 141)  
• 32 lead Ceramic Flatpack (Package 142)  
Single +5V (±10%) Supply Operation  
FIG. 1 PIN CONFIGURATION  
32 DIP  
32 SOJ  
32 CLCC  
32 FLATPACK  
PIN DESCRIPTION  
32 QUAD LCC  
TOP VIEW  
I/O0-7  
A0-16  
WE  
Data Inputs/Outputs  
Address Inputs  
Write Enable  
TOP VIEW  
4
3
2
1
32  
31 30  
NC  
A16  
A14  
A12  
A7  
A6  
A5  
A4  
A3  
A2 10  
A1 11  
AØ 12  
I/OØ 13  
I/O1 14  
I/O2 15  
1
2
3
4
5
6
7
8
9
32 VCC  
CS1, CS2  
OE  
Chip Selects  
31 A15  
30 CS2  
29 WE  
28 A13  
27 A8  
5
6
29  
28  
27  
26  
25  
24  
23  
22  
21  
A
7
6
5
4
3
2
1
0
0
WE  
Output Enable  
Power (+5V ±10%)  
Ground  
A
A
A
A
A
13  
VCC  
7
A
8
8
A
9
VSS  
26 A9  
9
A
11  
NC  
Not Connected  
25 A11  
24 OE  
23 A10  
22 CS1  
21 I/O7  
20 I/O6  
19 I/O5  
18 I/O4  
17 I/O3  
10  
11  
12  
13  
A
OE  
10  
CS  
I/O  
A
A
BLOCK DIAGRAM  
A
1
I/O  
7
Memory Array  
14  
15  
16  
17 18  
19  
20  
V
SS 16  
Address  
Buffer  
Address  
Decoder  
I/O  
Circuits  
A
Ø-16  
I/OØ-7  
WE  
CS  
1
CS2  
OE  
1
February 2000 Rev. 9  
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com  

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