Datasheet > EDI88130LPS17NC

EDI88130LPS17NC

更新时间： 2024-11-02 05:34:23

品牌	Logo	应用领域
美高森美 - MICROSEMI		静态存储器
页数	文件大小	规格书
9页	499K
描述
Standard SRAM, 128KX8, 17ns, CMOS, CDSO32, CERAMIC, SOJ-32

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中文翻译

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EDI88130LPS17NC 数据手册

EDI88130CS

White Electronic Designs

128Kx8 Monolithic SRAM, SMD 5962-89598

FEATURES

ꢀ

Access Times of 15*, 17, 20, 25, 35, 45, 55ns

ꢀ

Single +5V ( 10ꢀ) Supply OperationThe

EDI88130CS is a high speed, high performance,

128Kx8 bits monolithic Static RAM.

ꢀ

Battery Back-up Operation

• 2V Data Retention (EDI88130LPS)

CS1#, CS2 & OE# Functions for Bus Control

Inputs and Outputs Directly TTL Compatible

Organized as 128Kx8

Commercial, Industrial and Military Temperature

Ranges

ꢀ

An additional chip enable line provides system memory

security during power down in non-battery backed up

systems and memory banking in high speed battery

backed systems where large multiple pages of memory

are required.

ꢀ

Thru-hole and Surface Mount Packages JEDEC

Pinout

• 32 pin Sidebrazed Ceramic DIP, 400 mil

(Package 102)

• 32 pin Sidebrazed Ceramic DIP, 600 mil

(Package 9)

• 32 lead Ceramic SOJ (Package 140)

• 32 pad Ceramic Quad LCC (Package 12)

• 32 pad Ceramic LCC (Package 141)

• 32 lead Ceramic Flatpack (Package 142)

The EDI88130CS has eight bi-directional input-output lines

to provide simultaneous access to all bits in a word.

A low power version, EDI88130LPS, offers a 2V data

retention function for battery back-up applications.

Military product is available compliant to MIL-PRF-

38535.

* 15ns access time is advanced information, contact factory for availability.

FIGURE 1 – PIN CONFIGURATION

32 DIP

PIN DESCRIPTION

32 QUAD LCC

TOP VIEW

32 SOJ

I/O0-7

Data Input/Output

Address Inputs

Write Enable

Chip Select

Output Enable

Power Supply

Ground

32 CLCC

32 FLATPACK

A0-16

WE#

CS1#, CS2

OE#

TOP VIEW

31 30

I/O0

WE#

A13

V_CC

V_SS

A16

A14

A12

32 V_CC

31 A15

30 CS2#

29 WE#

28 A13

27 A8

Not Connected

A11

OE#

A10

CS1#

I/O7

26 A9

25 A11

24 OE#

23 A10

22 CS1#

Block Diagram

A2 10

A1 11

A0 12

I/O0 13

I/O1 14

I/O2 15

V_SS16

Memory Array

21 I/O7

17 18

20 I/O6

19 I/O5

18 I/O4

17 I/O3

Address

Buffer

Address

Decoder

I/O

Circuits

A0-16

I/O0-7

WE#

CS1#

CS2

OE#

White Electronic Designs Corp. reserves the right to change products or speciﬁcations without notice.

March 2002

Rev. 11

White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

12 3 4 5 6 7...9

中文翻译

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与EDI88130LPS17NC相关器件

型号	品牌	获取价格	描述	数据表
EDI88130LPS17NI	MICROSEMI	获取价格	Standard SRAM, 128KX8, 17ns, CMOS, CDSO32, CERAMIC, SOJ-32
EDI88130LPS17NM	MICROSEMI	获取价格	Standard SRAM, 128KX8, 17ns, CMOS, CDSO32, CERAMIC, SOJ-32
EDI88130LPS17TB	MICROSEMI	获取价格	Standard SRAM, 128KX8, 17ns, CMOS, CDIP32, 0.400 INCH, SIDE BRAZED, CERAMIC, DIP-32
EDI88130LPS17TC	MICROSEMI	获取价格	Standard SRAM, 128KX8, 17ns, CMOS, CDIP32, 0.400 INCH, SIDE BRAZED, CERAMIC, DIP-32
EDI88130LPS17TI	MICROSEMI	获取价格	Standard SRAM, 128KX8, 17ns, CMOS, CDIP32, 0.400 INCH, SIDE BRAZED, CERAMIC, DIP-32
EDI88130LPS20CB	MICROSEMI	获取价格	Standard SRAM, 128KX8, 20ns, CMOS, CDIP32, 0.600 INCH, SIDE BRAZED, CERAMIC, DIP-32
EDI88130LPS20CC	MICROSEMI	获取价格	Standard SRAM, 128KX8, 20ns, CMOS, CDIP32, 0.600 INCH, SIDE BRAZED, CERAMIC, DIP-32
EDI88130LPS20CI	MICROSEMI	获取价格	Standard SRAM, 128KX8, 20ns, CMOS, CDIP32, 0.600 INCH, SIDE BRAZED, CERAMIC, DIP-32
EDI88130LPS20CM	MICROSEMI	获取价格	Standard SRAM, 128KX8, 20ns, CMOS, CDIP32, 0.600 INCH, SIDE BRAZED, CERAMIC, DIP-32
EDI88130LPS20FB	MICROSEMI	获取价格	Standard SRAM, 128KX8, 20ns, CMOS, CDFP32, CERAMIC, FP-32

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