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EDI88130LPS17TC PDF预览

EDI88130LPS17TC

更新时间: 2024-11-01 14:41:59
品牌 Logo 应用领域
美高森美 - MICROSEMI 静态存储器
页数 文件大小 规格书
9页 499K
描述
Standard SRAM, 128KX8, 17ns, CMOS, CDIP32, 0.400 INCH, SIDE BRAZED, CERAMIC, DIP-32

EDI88130LPS17TC 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Active零件包装代码:DIP
包装说明:DIP, DIP32,.4针数:32
Reach Compliance Code:compliantECCN代码:3A991.B.2.B
HTS代码:8542.32.00.41风险等级:5.2
最长访问时间:17 nsI/O 类型:COMMON
JESD-30 代码:R-CDIP-T32长度:40.64 mm
内存密度:1048576 bit内存集成电路类型:STANDARD SRAM
内存宽度:8功能数量:1
端子数量:32字数:131072 words
字数代码:128000工作模式:ASYNCHRONOUS
最高工作温度:70 °C最低工作温度:
组织:128KX8输出特性:3-STATE
封装主体材料:CERAMIC, METAL-SEALED COFIRED封装代码:DIP
封装等效代码:DIP32,.4封装形状:RECTANGULAR
封装形式:IN-LINE并行/串行:PARALLEL
峰值回流温度(摄氏度):NOT SPECIFIED电源:5 V
认证状态:Not Qualified座面最大高度:3.937 mm
最大待机电流:0.002 A最小待机电流:2 V
子类别:SRAMs最大压摆率:0.3 mA
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:NO
技术:CMOS温度等级:COMMERCIAL
端子形式:THROUGH-HOLE端子节距:2.54 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:10.16 mmBase Number Matches:1

EDI88130LPS17TC 数据手册

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EDI88130CS  
White Electronic Designs  
128Kx8 Monolithic SRAM, SMD 5962-89598  
FEATURES  
Access Times of 15*, 17, 20, 25, 35, 45, 55ns  
Single +5V ( 10ꢀ) Supply OperationThe  
EDI88130CS is a high speed, high performance,  
128Kx8 bits monolithic Static RAM.  
Battery Back-up Operation  
• 2V Data Retention (EDI88130LPS)  
CS1#, CS2 & OE# Functions for Bus Control  
Inputs and Outputs Directly TTL Compatible  
Organized as 128Kx8  
Commercial, Industrial and Military Temperature  
Ranges  
An additional chip enable line provides system memory  
security during power down in non-battery backed up  
systems and memory banking in high speed battery  
backed systems where large multiple pages of memory  
are required.  
Thru-hole and Surface Mount Packages JEDEC  
Pinout  
• 32 pin Sidebrazed Ceramic DIP, 400 mil  
(Package 102)  
• 32 pin Sidebrazed Ceramic DIP, 600 mil  
(Package 9)  
• 32 lead Ceramic SOJ (Package 140)  
• 32 pad Ceramic Quad LCC (Package 12)  
• 32 pad Ceramic LCC (Package 141)  
• 32 lead Ceramic Flatpack (Package 142)  
The EDI88130CS has eight bi-directional input-output lines  
to provide simultaneous access to all bits in a word.  
A low power version, EDI88130LPS, offers a 2V data  
retention function for battery back-up applications.  
Military product is available compliant to MIL-PRF-  
38535.  
* 15ns access time is advanced information, contact factory for availability.  
FIGURE 1 – PIN CONFIGURATION  
32 DIP  
PIN DESCRIPTION  
32 QUAD LCC  
TOP VIEW  
32 SOJ  
I/O0-7  
Data Input/Output  
Address Inputs  
Write Enable  
Chip Select  
Output Enable  
Power Supply  
Ground  
32 CLCC  
32 FLATPACK  
A0-16  
WE#  
CS1#, CS2  
OE#  
TOP VIEW  
4
3
2
1
32  
31 30  
5
6
29  
28  
27  
26  
25  
24  
23  
22  
21  
A7  
A6  
A5  
A4  
A3  
A2  
A1  
A0  
I/O0  
WE#  
A13  
A8  
VCC  
VSS  
NC  
NC  
A16  
A14  
A12  
A7  
1
2
3
4
5
6
7
8
9
32 VCC  
31 A15  
30 CS2#  
29 WE#  
28 A13  
27 A8  
7
Not Connected  
8
A9  
9
A11  
OE#  
A10  
CS1#  
I/O7  
A6  
A5  
10  
11  
12  
13  
26 A9  
A4  
25 A11  
24 OE#  
23 A10  
22 CS1#  
Block Diagram  
A3  
A2 10  
A1 11  
A0 12  
I/O0 13  
I/O1 14  
I/O2 15  
VSS 16  
Memory Array  
21 I/O7  
14  
15  
16  
17 18  
19  
20  
20 I/O6  
19 I/O5  
18 I/O4  
17 I/O3  
Address  
Buffer  
Address  
Decoder  
I/O  
Circuits  
A0-16  
I/O0-7  
WE#  
CS1#  
CS2  
OE#  
White Electronic Designs Corp. reserves the right to change products or specifications without notice.  
March 2002  
Rev. 11  
1
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com  

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