EDI816256CA
HI-RELIABILITY PRODUCT
256Kx16 MONOLITHIC SRAM
FEATURES
■ 256Kx16 bit CMOS Static
The EDI816256CA is a 4 megabit Monolithic CMOS Static RAM.
The EDI816256CA uses 16 common input and output lines and has
an output enable pin which operates faster than address access
time at read cycle. The device allows upper and lower byte access
by use of the data byte control pins (LB, UB).
■ Random Access Memory
• Access Times of 17, 20, 25, 35ns
• Data Retention Function (LPA version)
• TTL Compatible Inputs and Outputs
• Fully Static, No Clocks
The devices are available in a fully hermetic 44 lead ceramic SOJ
and a 44 lead Ceramic Flatpack. The Ceramic SOJ is pin for pin
compatible with the commercially available plastic SOJ. This
allows the user the luxury of designing a board that can be used
for both the commercial and military market.
■ 44 lead JEDEC Approved Revolutionary Pinout
• Ceramic SOJ (Package 322)
• Ceramic Flatpack (Package 323)
■ Single +5V (±10%) Supply Operation
A Low Power version with Data Retention (EDI816256LPA) is also
available for battery backed applications. Military product is
available compliant to Appendix A of MIL-PRF-38535.
PIN CONFIGURATION
TOP VIEW
PIN DESCRIPTION
A0-17
LB (I/O1-8)
UB (I/O9-16)
I/O1-16
CS
Address Inputs
Lower-Byte Control (I/O1-8)
Upper-Byte Control (I/O9-16)
Data Input/Output
Chip Select
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
1
A0
A1
A17
A16
A15
OE
2
3
A2
4
A3
5
A4
UB
6
CS
LB
7
I/O1
I/O2
I/O3
I/O4
I/O16
I/O15
I/O14
I/O13
8
OE
Output Enable
9
WE
Write Enable
10
11
12
13
14
15
16
17
18
19
20
21
22
VCC
VSS
VCC
+5.0V Power
VSS
VCC
VSS
Ground
I/O5
I/O6
I/O7
I/O8
WE
A5
I/O12
I/O11
I/O10
I/O9
NC
NC
No Connection
A14
A13
A12
A11
A10
A6
A7
A8
A9
1
September 2000 Rev. 7
White Electronic Designs Corporation • Phoenix, AZ • (602) 437-1520