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EDI416S4030A

更新时间: 2024-09-20 03:06:39
品牌 Logo 应用领域
WEDC 动态存储器
页数 文件大小 规格书
27页 1123K
描述
1Mx16 Bits x 4 Banks Synchronous DRAM

EDI416S4030A 数据手册

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EDI416S4030A  
White Electronic Designs  
1Mx16 Bits x 4 Banks Synchronous DRAM  
FEATURES  
DESCRIPTION  
The EDI416S4030Ais 67,108,864 bits of synchronous high  
data rate DRAM organized as 4 x 1,048,576 words x 16 bits.  
Synchronous design allows precise cycle control with the  
use of system clock, I/O transactions are possible on every  
clock cycle. Range of operating frequencies, programmable  
burst lengths and programmable latencies allow the same  
device to be useful for a variety of high bandwidth, high  
performance memory system applications.  
Single 3.3V power supply  
Fully Synchronous to positive Clock Edge  
Clock Frequency = 100, 83MHz  
SDRAM CAS Latentency = 3 (100MHz), 2  
(83MHz)  
Burst Operation  
Sequential or Interleave  
Available in a 54 pin TSOP type II package the  
EDI416S4030A is tested over the industrial temp range (-  
40C to +85C) providing a solution for rugged main memory  
applications.  
Burst length = programmable 1,2,4,8 or full page  
Burst Read and Write  
Multiple Burst Read and Single Write  
DATA Mask Control per byte  
Auto Refresh (CBR) and Self Refresh  
4096 refresh cycles across 64ms  
Automatic and Controlled Precharge Commands  
Suspend Mode and Power Down Mode  
Industrial Temperature Range  
FIG. 1  
PIN CONFIGURATIONS  
PIN DESCRIPTION  
VCC  
DQ0  
VCCQ  
DQ1  
DQ2  
VSSQ  
DQ3  
DQ4  
VCCQ  
DQ5  
DQ6  
VSSQ  
DQ7  
VCC  
1
54  
53  
52  
51  
50  
49  
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
28  
VSS  
2
DQ15  
VSSQ  
DQ14  
DQ13  
VCCQ  
DQ12  
DQ11  
VSSQ  
DQ10  
DQ9  
VCCQ  
DQ8  
VSS  
A0-11  
BA0, BA1  
CE#  
Address Inputs  
Bank Select Address  
Chip Select  
3
4
5
6
WE#  
Write Enable  
7
CK  
Clock Input  
8
9
CKE  
Clock Enable  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
DQ0-15  
L(U)DQM  
RAS#  
CAS#  
Data Input/Output  
Data Input/Output Mask  
Row Address Strobe  
Column Address Strobe  
Power (+3.3V ±10%)  
Data Output Power  
Ground  
LDQM  
WE#  
CAS#  
RAS#  
CE#  
BA0  
NC/RFU  
UDQM  
CK  
V
CC  
V
CCQ  
CKE  
NC  
V
SS  
A11  
V
SSQ  
Data Output Ground  
No Connection  
BA1  
A9  
NC  
A10/AP  
A0  
A8  
A7  
A1  
A6  
A2  
A5  
A3  
A4  
VCC  
VSS  
White Electronic Designs Corp. reserves the right to change products or specifications without notice.  
January, 2003  
1
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com  
Rev. 2  

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