Datasheet > EDI416S4030A-SI

EDI416S4030A-SI

更新时间： 2024-09-20 23:50:03

品牌	Logo	应用领域
其他 - ETC		动态存储器
页数	文件大小	规格书
27页	319K
描述
Industrial SDRAM

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EDI416S4030A-SI 数据手册

EDI416S4030A

White Electronic Designs

1M x 16 Bits x 4 Banks Synchronous DRAM

DESCRIPTION

FEATURES

The EDI416S4030A is 67,108,864 bits of synchronous high

data rate DRAM organized as 4 x 1,048,576 words x 16

bits. Synchronous design allows precise cycle control with

the use of system clock, I/O transactions are possible on

every clock cycle. Range of operating frequencies, program-

mable burst lengths and programmable latencies allow the

same device to be useful for a variety of high bandwidth,

high performance memory system applications.

Single 3.3V power supply

Fully Synchronous to positive Clock Edge

Clock Frequency = 100, 83MHz

SDRAM CAS Latentency = 3 (100MHz), 2 (83MHz)

Burst Operation

•Sequential or Interleave

•Burst length = programmable 1,2,4,8 or full page

•Burst Read and Write

Available in a 54 pin TSOP type II package the EDI416S4030A

is tested over the industrial temp range (-40C to +85C)

providing a solution for rugged main memory applications.

•Multiple Burst Read and Single Write

DATA Mask Control per byte

Auto Refresh (CBR) and Self Refresh

•4096 refresh cycles across 64ms

Automatic and Controlled Precharge Commands

Suspend Mode and Power Down Mode

Industrial Temperature Range

FIGꢀ 1

PIN CONFIGURATION

DQ15

SSQ

DDQ

DQ14

DQ13

VDDQ

DQ12

DQ11

PIN DESCRIPTION

A_0-11

BA₀, BA₁

Address Inputs

Bank Select Addresses

Chip Select

SSQ

DDQ

SSQ

DQ10

Write Enable

CLK

Clock Input

CKE

Clock Enable

SSQ

VDDQ

DQ8

VSS

NC/RFU

UDQM

CLK

CKE

LDQM

CAS

RAS

10/AP

DQ_0-15

Data Input/Output

L(U)DQM Data Input/Output Mask

RAS

CAS

VDD

VDDQ

VSS

Row Address Strobe

Column Address Strobe

Power (3.3V)

Data Output Power

Ground

VSSQ

Data Output Ground

No Connection

January 2003 Rev.2

ECO # 14194

White Electronic Designs Corporation • (508) 366-5151 • www.whiteedc.com

12 3 4 5 6 7...27

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