EBE52UD6ABSA-5C-E

更新时间： 2024-11-06 22:12:47

品牌	Logo	应用领域
尔必达 - ELPIDA		动态存储器双倍数据速率
页数	文件大小	规格书
21页	228K
描述
512MB DDR2 SDRAM SO-DIMM (64M words x 64 bits, 2 Ranks)

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DATA SHEET

512MB DDR2 SDRAM SO-DIMM

EBE52UD6ABSA (64M words × 64 bits, 2 Ranks)

Description

Features

The EBE52UD6ABSA is 64M words × 64 bits, 2 ranks

DDR2 SDRAM Small Outline Dual In-line Memory

Module, mounting 8 pieces of 512M bits DDR2

SDRAM sealed in FBGA (µBGA^) package. Read and

write operations are performed at the cross points of

the CK and the /CK. This high-speed data transfer is

realized by the 4 bits prefetch-pipelined architecture.

Data strobe (DQS and /DQS) both for read and write

are available for high speed and reliable data bus

design. By setting extended mode register, the on-chip

Delay Locked Loop (DLL) can be set enable or disable.

This module provides high density mounting without

• 200-pin socket type small outline dual in line memory

module (SO-DIMM)

PCB height: 30.0mm

Lead pitch: 0.6mm

Lead-free

• 1.8V power supply

• Data rate: 533Mbps/400Mbps (max.)

• 1.8V (SSTL_18 compatible) I/O

• Double-data-rate architecture: two data transfers per

clock cycle

• Bi-directional, differential data strobe (DQS and

/DQS) is transmitted/received with data, to be used in

capturing data at the receiver

utilizing surface mount technology.

Decoupling

capacitors are mounted beside each FBGA (µBGA) on

the module board.

• DQS is edge aligned with data for READs: center-

aligned with data for WRITEs

Note: Do not push the components or drop the

modules in order to avoid mechanical defects,

which may result in electrical defects.

• Differential clock inputs (CK and /CK)

• DLL aligns DQ and DQS transitions with CK

transitions

• Commands entered on each positive CK edge: data

and data mask referenced to both edges of DQS

• Four internal banks for concurrent operation

(Component)

• Data mask (DM) for write data

• Burst lengths: 4, 8

• /CAS Latency (CL): 3, 4, 5

• Auto precharge operation for each burst access

• Auto refresh and self refresh modes

• 7.8µs average periodic refresh interval

• Posted CAS by programmable additive latency for

better command and data bus efficiency

• Off-Chip-Driver Impedance Adjustment and On-Die-

Termination for better signal quality

• /DQS can be disabled for single-ended Data Strobe

operation.

Document No. E0418E30 (Ver. 3.0)

Date Published June 2004 (K) Japan

URL: http://www.elpida.com

Elpida Memory, Inc. 2003-2004

12 3 4 5 6 7...21

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与EBE52UD6ABSA-5C-E相关器件

型号	品牌	获取价格	描述	数据表
EBE52UD6AFSA	ELPIDA	获取价格	512MB DDR2 SDRAM SO-DIMM (64M words x 64 bits, 2 Ranks)
EBE52UD6AFSA-4A-E	ELPIDA	获取价格	512MB DDR2 SDRAM SO-DIMM (64M words x 64 bits, 2 Ranks)
EBE52UD6AFSA-5C-E	ELPIDA	获取价格	512MB DDR2 SDRAM SO-DIMM (64M words x 64 bits, 2 Ranks)
EBE52UD6AFSA-6E-E	ELPIDA	获取价格	512MB DDR2 SDRAM SO-DIMM (64M words x 64 bits, 2 Ranks)
EBE52UD6AHUA-5C-E	ELPIDA	获取价格	DDR DRAM Module, 64MX64, 0.5ns, CMOS, ROHS COMPLIANT, SODIMM-200
EBE52UD6AHUA-6E-E	ELPIDA	获取价格	DDR DRAM Module, 64MX64, 0.45ns, CMOS, ROHS COMPLIANT, SODIMM-200
EBE52UD6AJUA	ELPIDA	获取价格	512MB DDR2 SDRAM SO-DIMM
EBE52UD6AJUA-6E-E	ELPIDA	获取价格	512MB DDR2 SDRAM SO-DIMM
EBE52UD6AJUA-8E-E	ELPIDA	获取价格	512MB DDR2 SDRAM SO-DIMM
EBE52UD6AJUA-8G-E	ELPIDA	获取价格	512MB DDR2 SDRAM SO-DIMM

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