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DTA115EM3T5G

更新时间: 2024-02-02 19:19:38
品牌 Logo 应用领域
安森美 - ONSEMI 晶体小信号双极晶体管数字晶体管开关光电二极管
页数 文件大小 规格书
12页 124K
描述
Digital Transistors (BRT) PNP Silicon Surface Mount Transistors with Monolithic Bias Resistor Network

DTA115EM3T5G 技术参数

是否无铅: 不含铅生命周期:Active
包装说明:SMALL OUTLINE, R-PDSO-F3针数:3
Reach Compliance Code:compliantECCN代码:EAR99
Factory Lead Time:2 weeks风险等级:1.23
Is Samacsys:N其他特性:BUILT-IN BIAS RESISTOR RATIO IS 1
最大集电极电流 (IC):0.1 A集电极-发射极最大电压:50 V
配置:SINGLE WITH BUILT-IN RESISTOR最小直流电流增益 (hFE):80
JESD-30 代码:R-PDSO-F3JESD-609代码:e3
湿度敏感等级:1元件数量:1
端子数量:3最高工作温度:150 °C
封装主体材料:PLASTIC/EPOXY封装形状:RECTANGULAR
封装形式:SMALL OUTLINE峰值回流温度(摄氏度):260
极性/信道类型:PNP最大功率耗散 (Abs):0.6 W
认证状态:Not Qualified子类别:BIP General Purpose Small Signal
表面贴装:YES端子面层:Tin (Sn)
端子形式:FLAT端子位置:DUAL
处于峰值回流温度下的最长时间:40晶体管应用:SWITCHING
晶体管元件材料:SILICONBase Number Matches:1

DTA115EM3T5G 数据手册

 浏览型号DTA115EM3T5G的Datasheet PDF文件第2页浏览型号DTA115EM3T5G的Datasheet PDF文件第3页浏览型号DTA115EM3T5G的Datasheet PDF文件第4页浏览型号DTA115EM3T5G的Datasheet PDF文件第5页浏览型号DTA115EM3T5G的Datasheet PDF文件第6页浏览型号DTA115EM3T5G的Datasheet PDF文件第7页 
DTA114EM3T5G Series  
Preferred Devices  
Digital Transistors (BRT)  
PNP Silicon Surface Mount Transistors  
with Monolithic Bias Resistor Network  
This new series of digital transistors is designed to replace a single  
device and its external resistor bias network. The digital transistor  
contains a single transistor with a monolithic bias network consisting  
of two resistors; a series base resistor and a base−emitter resistor. The  
digital transistor eliminates these individual components by  
integrating them into a single device. The use of a digital transistor can  
reduce both system cost and board space. The device is housed in the  
SOT−723 package which is designed for low power surface mount  
applications.  
http://onsemi.com  
PNP SILICON  
DIGITAL  
TRANSISTORS  
Simplifies Circuit Design  
Reduces Board Space  
Reduces Component Count  
The SOT−723 Package can be Soldered using Wave or Reflow.  
Available in 4 mm, 8000 Unit Tape & Reel  
These are Pb−Free Devices  
PIN 3  
COLLECTOR  
(OUTPUT)  
PIN 1  
BASE  
(INPUT)  
R1  
R2  
PIN 2  
EMITTER  
(GROUND)  
MAXIMUM RATINGS (T = 25°C unless otherwise noted)  
A
Rating  
Collector-Base Voltage  
Collector-Emitter Voltage  
Collector Current  
Symbol  
Value  
50  
Unit  
Vdc  
MARKING  
DIAGRAM  
V
CBO  
CEO  
V
50  
Vdc  
3
I
C
100  
mAdc  
XX M  
SOT−723  
CASE 631AA  
Style 1  
2
1
xx = Specific Device Code  
(See Marking Table on page 2)  
M
= Date Code  
ORDERING INFORMATION  
See detailed ordering and shipping information in the package  
dimensions section on page 2 of this data sheet.  
Preferred devices are recommended choices for future use  
and best overall value.  
Semiconductor Components Industries, LLC, 2004  
1
Publication Order Number:  
February, 2004 − Rev. 0  
DTA114EM3/D  

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