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DS92LV3221TVS/NOPB PDF预览

DS92LV3221TVS/NOPB

更新时间: 2023-09-03 20:27:40
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德州仪器 - TI /
页数 文件大小 规格书
31页 950K
描述
20-50MHz 32 位频道链接 II 串行器 | PAG | 64 | -40 to 85

DS92LV3221TVS/NOPB 数据手册

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DS92LV3221, DS92LV3222  
www.ti.com  
SNLS319C OCTOBER 2009REVISED APRIL 2013  
DS92LV3221/DS92LV3222 20-50 MHz 32-Bit Channel Link II Serializer / Deserializer  
Check for Samples: DS92LV3221, DS92LV3222  
1
FEATURES  
APPLICATIONS  
2
Wide Operating Range Embedded Clock  
SER/DES  
Industrial Imaging (Machine-vision) and  
Control  
Up to 32-bit Parallel LVCMOS Data  
20 to 50 MHz Parallel Clock  
Security and Surveillance Cameras and  
Infrastructure  
Medical Imaging  
Up to 1.6 Gbps Application Data Paylod  
Simplified Clocking Architecture  
DESCRIPTION  
No Separate Serial Clock Line  
No Reference Clock Required  
Receiver Locks to Random Data  
The DS92LV3221 (SER) serializes a 32-bit data bus  
into 2 embedded clock LVDS serial channels for a  
data payload rate up to 1.6 Gbps over cables such as  
CATx, or backplanes FR-4 traces. The companion  
DS92LV3222 (DES) deserializes the 2 LVDS serial  
data channels, de-skews channel-to-channel delay  
variations and converts the LVDS data stream back  
into a 32-bit LVCMOS parallel data bus.  
On-chip Signal Conditioning for Robust Serial  
Connectivity  
Transmit Pre-Emphasis  
Data Randomization  
DC-Balance Encoding  
On-chip data Randomization/Scrambling and DC  
balance encoding and selectable serializer Pre-  
emphasis ensure a robust, low-EMI transmission over  
longer, lossy cables and backplanes. The  
Deserializer automatically locks to incoming data  
without an external reference clock or special sync  
patterns, providing an easy “plug-and-lock” operation.  
Receive Channel Deskew  
Supports up to 10m CAT-5 at 1.6Gbps  
Integrated LVDS Terminations  
Built-in AT-SPEED BIST for End-To-End  
System Testing  
AC-Coupled Interconnect for Isolation and  
Fault Protection  
By embedding the clock in the data payload and  
including signal conditioning functions, the Channel-  
Link II SerDes devices reduce trace count, eliminate  
skew issues, simplify design effort and lower  
cable/connector cost for a wide variety of video,  
control and imaging applications. A built-in AT-  
SPEED BIST feature validates link integrity and may  
be used for system diagnostics.  
> 4KV HBM ESD Protection  
Space-Saving 64-pin TQFP Package  
Full Industrial Temperature Range: -40° to  
+85°C  
BLOCK DIAGRAM  
High-Speed  
Serial Data  
RxCLKOUT  
RxOUT0  
CDR/PLL  
PLL  
TxCLKIN  
TxIN0  
100W differential pairs  
RxIN0+  
TxOUT0+  
RxOUT15  
RxOUT16  
TxIN15  
TxIN16  
TxOUT0 -  
TxOUT1+  
RxIN0 -  
RxIN1 +  
RxOUT31  
LOCK  
TxIN31  
TxOUT1 -  
RxIN1 -  
PDB  
R_FB  
BIST  
BIST  
BISTEN  
MODE  
VSEL  
REN  
Control  
R_FB  
Control  
Pre-Emp  
PRE  
PDB  
Tx - SERIALIZER  
Rx - DESERIALIZER  
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
2
All trademarks are the property of their respective owners.  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
Copyright © 2009–2013, Texas Instruments Incorporated  

DS92LV3221TVS/NOPB 替代型号

型号 品牌 替代类型 描述 数据表
DS92LV3221TVSX/NOPB TI

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