September 17, 2009
DS92LV3241/DS92LV3242
20-85 MHz 32-Bit Channel Link II Serializer/Deserializer
Dual Lane Mode (20 to 50 MHz)
Quad Lane Mode (40 to 85 MHz)
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General Description
The DS92LV3241 (SER) serializes a 32-bit data bus into 2 or
4 (selectable) embedded clock LVDS serial channels for a
data payload rate up to 2.72 Gbps over cables such as CATx,
or backplanes FR-4 traces. The companion DS92LV3242
(DES) deserializes the 2 or 4 LVDS serial data channels, de-
skews channel-to-channel delay variations and converts the
LVDS data stream back into a 32-bit LVCMOS parallel data
bus.
Simplified Clocking Architecture
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No separate serial clock line
No reference clock required
Receiver locks to random data
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On-chip Signal Conditioning for Robust Serial
Connectivity
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Transmit Pre-Emphasis
Data randomization
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On-chip data Randomization/Scrambling and DC balance en-
coding and selectable serializer Pre-emphasis ensure a ro-
bust, low-EMI transmission over longer, lossy cables and
backplanes. The Deserializer automatically locks to incoming
data without an external reference clock or special sync pat-
terns, providing an easy “plug-and-lock” operation.
DC-balance encoding
Receive channel deskew
Supports up to 10m CAT-5 at 2.7 Gbps
Integrated LVDS Terminations
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By embedding the clock in the data payload and including
signal conditioning functions, the Channel-Link II SerDes de-
vices reduce trace count, eliminate skew issues, simplify
design effort and lower cable/connector cost for a wide variety
of video, control and imaging applications. A built-in AT-
SPEED BIST feature validates link integrity and may be used
for system diagnostics.
Built-in AT-SPEED BIST for end-to-end system testing
AC-coupled interconnect for isolation and fault protection
> 4KV HBM ESD protection
Space-saving 64-pin TQFP package
Full industrial temperature range : -40° to +85°C
Applications
Features
Industrial imaging (Machine-vision) and control
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Wide Operating Range Embedded Clock SER/DES
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Security & Surveillance cameras and infrastructure
Up to 32-bit parallel LVCMOS data
20 to 85 MHz parallel clock
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Medical imaging
Up to 30 bits per pixel, VGA to HD video transport and
Up to 2.72 Gbps application data paylod
display
Selectable Serial LVDS Bus Width
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