DS92LV0411, DS92LV0412
www.ti.com
SNLS331B –MAY 2010–REVISED APRIL 2013
DS92LV0411 / DS92LV0412 5 - 50 MHz Channel Link II Serializer/Deserializer with LVDS
Parallel Interface
Check for Samples: DS92LV0411, DS92LV0412
1
FEATURES
DESCRIPTION
The DS92LV0411 (serializer) and DS92LV0412
(deserializer) chipset translates a Channel Link LVDS
video interface (4 LVDS Data + LVDS Clock) into a
high-speed serialized interface over a single CML
pair.
2
•
5-Channel (4 data + 1 clock) Channel Link
LVDS Parallel Interface Supports 24-bit Data
3-bit Control at 5 – 50 MHz
•
AC Coupled STP Interconnect up to 10 Meters
in Length
The DS92LV0411/DS92LV0412 enables applications
that currently use the popular Channel Link or
Channel Link style devices to seamlessly upgrade to
an embedded clock interface to reduce interconnect
cost or ease design challenges. The parallel LVDS
interface also reduces FPGA I/O pins, board trace
count and alleviates EMI issues, when compared to
traditional single-ended wide bus interfaces.
•
•
•
•
Integrated Serial CML Terminations
AT–SPEED BIST Mode and Status Pin
Optional I2C Compatible Serial Control Bus
Power Down Mode Minimizes Power
Dissipation
•
•
•
1.8V or 3.3V Compatible Control Pin Interface
>8 kV ESD (HBM) Protection
Programmable
transmit
de-emphasis,
receive
-40° to +85°C Temperature Range
SERIALIZER – DS92LV0411
equalization, on-chip scrambling and DC balancing
enables longer distance transmission over lossy
cables
and
backplanes.
The
Deserializer
•
•
•
Data Scrambler for Reduced EMI
DC–Balance Encoder for AC Coupling
automatically locks to incoming data without an
external reference clock or special sync patterns,
providing easy “plug-and-go” operation.
Selectable Output VOD and Adjustable De-
Emphasis
The
DS92LV0411
and
DS92LV0412
are
programmable though an I2C interface as well as by
pins. A built-in AT-SPEED BIST feature validates link
integrity and may be used for system diagnostics.
DESERIALIZER – DS92LV0412
•
Random Data Lock; No Reference Clock
Required
The DS92LV0411 and DS92LV0412 can be used
•
•
Adjustable Input Receiver Equalization
interchangeably
with
the
DS92LV2411
or
EMI Minimization on Output Parallel Bus
(Spread Spectrum Clock Generation and LVDS
VOD Select)
DS92LV2412. This allows designers the flexibility to
connect to the host device and receiving devices with
different interface types, LVDS or LVCMOS.
APPLICATIONS
•
•
Embedded Video and Display
Machine Vision, Industrial Imaging, Medical
Imaging
•
Office Automation — Printers, Scanners,
Copiers
•
•
Security and Video Surveillance
General purpose data communication
1
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2
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PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
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