DS92LV0412SQNOPB

更新时间： 2024-11-21 13:07:27

品牌	Logo	应用领域
美国国家半导体 - NSC		/
页数	文件大小	规格书
40页	943K
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数据手册

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DS92LV0412SQNOPB 数据手册

PRELIMINARY

May 26, 2010

DS92LV0411 / DS92LV0412

5 - 50 MHz Channel Link II Serializer/Deserializer with LVDS

Parallel Interface

General Description

Features

5-channel (4 data + 1 clock) Channel Link LVDS parallel

■

The DS92LV0411 (serializer) and DS92LV0412 (deserializer)

chipset translates a Channel Link LVDS video interface (4

LVDS Data + LVDS Clock) into a high-speed serialized inter-

face over a single CML pair.

interface supports 24-bit data 3-bit control at 5 – 50 MHz

AC Coupled STP Interconnect up to 10 meters in length

■

Integrated serial CML terminations

The DS92LV0411/DS92LV0412 enables applications that

currently use the popular Channel Link or Channel Link style

devices to seamlessly upgrade to an embedded clock inter-

face to reduce interconnect cost or ease design challenges.

The parallel LVDS interface also reduces FPGA I/O pins,

board trace count and alleviates EMI issues, when compared

to traditional single-ended wide bus interfaces.

AT–SPEED BIST Mode and status pin

Optional I2C compatible Serial Control Bus

Power Down Mode minimizes power dissipation

1.8V or 3.3V compatible control pin interface

>8 kV ESD (HBM) protection

-40° to +85°C temperature range

Programmable transmit de-emphasis, receive equalization,

on-chip scrambling and DC balancing enables longer dis-

tance transmission over lossy cables and backplanes. The

Deserializer automatically locks to incoming data without an

external reference clock or special sync patterns, providing

easy “plug-and-go” operation.

SERIALIZER – DS92LV0411

Data scrambler for reduced EMI

■

DC–balance encoder for AC coupling

Selectable output VOD and adjustable de-emphasis

DESERIALIZER – DS92LV0412

The DS92LV0411 and DS92LV0412 are programmable

though an I2C interface as well as by pins. A built-in AT-

SPEED BIST feature validates link integrity and may be used

for system diagnostics.

Random data lock; no reference clock required

■

Adjustable input receiver equalization

EMI minimization on output parallel bus (Spread Spectrum

Clock Generation and LVDS VOD select)

The DS92LV0411 and DS92LV0412 can be used inter-

changeably with the DS92LV2411 or DS92LV2412. This al-

lows designers the flexibility to connect to the host device and

receiving devices with different interface types, LVDS or LVC-

MOS.

Applications

Embedded Video and Display

■

Machine Vision, Industrial Imaging, Medical Imaging

Office Automation — Printers, Scanners, Copiers

Security and Video Surveillance

General purpose data communication

■

Applications Diagram

30125227

TRI-STATE® is a registered trademark of National Semiconductor Corporation.

301252

www.national.com

12 3 4 5 6 7...40

中文翻译

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与DS92LV0412SQNOPB相关器件

型号	品牌	获取价格	描述	数据表
DS92LV0412SQX	NSC	获取价格	5 - 50 MHz Channel Link II Serializer/Deserializer with LVDS Parallel Interface
DS92LV0412SQX/NOPB	TI	获取价格	具有 LVDS 并行接口的 5 - 50MHz Channel Link II 解串器 \|
DS92LV0412SQXNOPB	NSC	获取价格	暂无描述
DS92LV0421	NSC	获取价格	10 - 75 MHz Channel Link II Serializer/Deserializer with LVDS Parallel Interface
DS92LV0421	TI	获取价格	具有 LVDS 并行接口的 10MHz 至 75MHz Channel-Link II 串
DS92LV0421SQ	NSC	获取价格	10 - 75 MHz Channel Link II Serializer/Deserializer with LVDS Parallel Interface
DS92LV0421SQ/NOPB	NSC	获取价格	IC LINE DRIVER, QCC36, 6 X 6 MM, 0.80 MM HEIGHT, 0.50 MM PITCH, ROHS COMPLIANT, LLP-36, Li
DS92LV0421SQ/NOPB	TI	获取价格	具有 LVDS 并行接口的 10MHz 至 75MHz Channel-Link II 串
DS92LV0421SQE	NSC	获取价格	10 - 75 MHz Channel Link II Serializer/Deserializer with LVDS Parallel Interface
DS92LV0421SQE/NOPB	NSC	获取价格	IC LINE DRIVER, QCC36, 6 X 6 MM, 0.80 MM HEIGHT, 0.50 MM PITCH, ROHS COMPLIANT, LLP-36, Li

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