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DS92LV0412SQX PDF预览

DS92LV0412SQX

更新时间: 2024-01-14 05:49:24
品牌 Logo 应用领域
美国国家半导体 - NSC 线路驱动器或接收器驱动程序和接口接口集成电路
页数 文件大小 规格书
40页 943K
描述
5 - 50 MHz Channel Link II Serializer/Deserializer with LVDS Parallel Interface

DS92LV0412SQX 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active包装说明:HVQCCN, LCC48,.27SQ,20
Reach Compliance Code:compliantECCN代码:5A991.B.1
HTS代码:8542.39.00.01风险等级:5.11
差分输出:NO接口集成电路类型:LINE DRIVER
JESD-30 代码:S-PQCC-N48JESD-609代码:e3
长度:7 mm湿度敏感等级:3
功能数量:1端子数量:48
最高工作温度:85 °C最低工作温度:-40 °C
输出特性:3-STATE输出极性:TRUE
封装主体材料:PLASTIC/EPOXY封装代码:HVQCCN
封装等效代码:LCC48,.27SQ,20封装形状:SQUARE
封装形式:CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE峰值回流温度(摄氏度):260
电源:1.8,3.3 V认证状态:Not Qualified
最大接收延迟:接收器位数:1
座面最大高度:0.8 mm子类别:Line Driver or Receivers
最大压摆率:95 mA标称供电电压:1.8 V
电源电压1-最大:1.89 V电源电压1-分钟:1.71 V
电源电压1-Nom:1.8 V表面贴装:YES
温度等级:INDUSTRIAL端子面层:Matte Tin (Sn)
端子形式:NO LEAD端子节距:0.5 mm
端子位置:QUAD处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:7 mmBase Number Matches:1

DS92LV0412SQX 数据手册

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PRELIMINARY  
May 26, 2010  
DS92LV0411 / DS92LV0412  
5 - 50 MHz Channel Link II Serializer/Deserializer with LVDS  
Parallel Interface  
General Description  
Features  
5-channel (4 data + 1 clock) Channel Link LVDS parallel  
The DS92LV0411 (serializer) and DS92LV0412 (deserializer)  
chipset translates a Channel Link LVDS video interface (4  
LVDS Data + LVDS Clock) into a high-speed serialized inter-  
face over a single CML pair.  
interface supports 24-bit data 3-bit control at 5 – 50 MHz  
AC Coupled STP Interconnect up to 10 meters in length  
Integrated serial CML terminations  
The DS92LV0411/DS92LV0412 enables applications that  
currently use the popular Channel Link or Channel Link style  
devices to seamlessly upgrade to an embedded clock inter-  
face to reduce interconnect cost or ease design challenges.  
The parallel LVDS interface also reduces FPGA I/O pins,  
board trace count and alleviates EMI issues, when compared  
to traditional single-ended wide bus interfaces.  
AT–SPEED BIST Mode and status pin  
Optional I2C compatible Serial Control Bus  
Power Down Mode minimizes power dissipation  
1.8V or 3.3V compatible control pin interface  
>8 kV ESD (HBM) protection  
-40° to +85°C temperature range  
Programmable transmit de-emphasis, receive equalization,  
on-chip scrambling and DC balancing enables longer dis-  
tance transmission over lossy cables and backplanes. The  
Deserializer automatically locks to incoming data without an  
external reference clock or special sync patterns, providing  
easy “plug-and-go” operation.  
SERIALIZER – DS92LV0411  
Data scrambler for reduced EMI  
DC–balance encoder for AC coupling  
Selectable output VOD and adjustable de-emphasis  
DESERIALIZER – DS92LV0412  
The DS92LV0411 and DS92LV0412 are programmable  
though an I2C interface as well as by pins. A built-in AT-  
SPEED BIST feature validates link integrity and may be used  
for system diagnostics.  
Random data lock; no reference clock required  
Adjustable input receiver equalization  
EMI minimization on output parallel bus (Spread Spectrum  
Clock Generation and LVDS VOD select)  
The DS92LV0411 and DS92LV0412 can be used inter-  
changeably with the DS92LV2411 or DS92LV2412. This al-  
lows designers the flexibility to connect to the host device and  
receiving devices with different interface types, LVDS or LVC-  
MOS.  
Applications  
Embedded Video and Display  
Machine Vision, Industrial Imaging, Medical Imaging  
Office Automation — Printers, Scanners, Copiers  
Security and Video Surveillance  
General purpose data communication  
Applications Diagram  
30125227  
TRI-STATE® is a registered trademark of National Semiconductor Corporation.  
© 2010 National Semiconductor Corporation  
301252  
www.national.com  

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