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DS92LV0411SQX/NOPB PDF预览

DS92LV0411SQX/NOPB

更新时间: 2024-11-26 11:12:43
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德州仪器 - TI /
页数 文件大小 规格书
53页 707K
描述
具有 LVDS 并行接口的 5 - 50MHz Channel Link II 串行器 | NJK | 36 | -40 to 85

DS92LV0411SQX/NOPB 数据手册

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DS92LV0411, DS92LV0412  
www.ti.com  
SNLS331B MAY 2010REVISED APRIL 2013  
DS92LV0411 / DS92LV0412 5 - 50 MHz Channel Link II Serializer/Deserializer with LVDS  
Parallel Interface  
Check for Samples: DS92LV0411, DS92LV0412  
1
FEATURES  
DESCRIPTION  
The DS92LV0411 (serializer) and DS92LV0412  
(deserializer) chipset translates a Channel Link LVDS  
video interface (4 LVDS Data + LVDS Clock) into a  
high-speed serialized interface over a single CML  
pair.  
2
5-Channel (4 data + 1 clock) Channel Link  
LVDS Parallel Interface Supports 24-bit Data  
3-bit Control at 5 – 50 MHz  
AC Coupled STP Interconnect up to 10 Meters  
in Length  
The DS92LV0411/DS92LV0412 enables applications  
that currently use the popular Channel Link or  
Channel Link style devices to seamlessly upgrade to  
an embedded clock interface to reduce interconnect  
cost or ease design challenges. The parallel LVDS  
interface also reduces FPGA I/O pins, board trace  
count and alleviates EMI issues, when compared to  
traditional single-ended wide bus interfaces.  
Integrated Serial CML Terminations  
AT–SPEED BIST Mode and Status Pin  
Optional I2C Compatible Serial Control Bus  
Power Down Mode Minimizes Power  
Dissipation  
1.8V or 3.3V Compatible Control Pin Interface  
>8 kV ESD (HBM) Protection  
Programmable  
transmit  
de-emphasis,  
receive  
-40° to +85°C Temperature Range  
SERIALIZER – DS92LV0411  
equalization, on-chip scrambling and DC balancing  
enables longer distance transmission over lossy  
cables  
and  
backplanes.  
The  
Deserializer  
Data Scrambler for Reduced EMI  
DC–Balance Encoder for AC Coupling  
automatically locks to incoming data without an  
external reference clock or special sync patterns,  
providing easy “plug-and-go” operation.  
Selectable Output VOD and Adjustable De-  
Emphasis  
The  
DS92LV0411  
and  
DS92LV0412  
are  
programmable though an I2C interface as well as by  
pins. A built-in AT-SPEED BIST feature validates link  
integrity and may be used for system diagnostics.  
DESERIALIZER – DS92LV0412  
Random Data Lock; No Reference Clock  
Required  
The DS92LV0411 and DS92LV0412 can be used  
Adjustable Input Receiver Equalization  
interchangeably  
with  
the  
DS92LV2411  
or  
EMI Minimization on Output Parallel Bus  
(Spread Spectrum Clock Generation and LVDS  
VOD Select)  
DS92LV2412. This allows designers the flexibility to  
connect to the host device and receiving devices with  
different interface types, LVDS or LVCMOS.  
APPLICATIONS  
Embedded Video and Display  
Machine Vision, Industrial Imaging, Medical  
Imaging  
Office Automation — Printers, Scanners,  
Copiers  
Security and Video Surveillance  
General purpose data communication  
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
2
All trademarks are the property of their respective owners.  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
Copyright © 2010–2013, Texas Instruments Incorporated  

DS92LV0411SQX/NOPB 替代型号

型号 品牌 替代类型 描述 数据表
DS92LV0411SQ/NOPB TI

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具有 LVDS 并行接口的 5 - 50MHz Channel Link II 串行器 |
DS92LV0411SQE/NOPB TI

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暂无描述
DS92LV0412SQX NSC

获取价格

5 - 50 MHz Channel Link II Serializer/Deserializer with LVDS Parallel Interface