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DS92001TLD

更新时间： 2024-11-20 22:10:27

品牌	Logo	应用领域
美国国家半导体 - NSC		/
页数	文件大小	规格书
12页	255K
描述
3.3V B/LVDS-BLVDS Buffer

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DS92001TLD 数据手册

June 2002

DS92001

3.3V B/LVDS-BLVDS Buffer

General Description

The LOS pin detects a non-driven B/LVDS bus state at the

input and provides an active LOW output. The LOS pin can

be tied to the device’s output enable pin (EN) to generate a

TRI-STATE output state when the input is un-driven. The

LOS pin can also be used locally to inform the system of the

bus state.

The DS92001 B/LVDS-BLVDS Buffer takes a BLVDS input

signal and provides an BLVDS output signal. In many large

systems, signals are distributed across backplanes, and one

of the limiting factors for system speed is the ’stub length’ or

the distance between the transmission line and the untermi-

nated receivers on individual cards. Although it is generally

recognized that this distance should be as short as possible

to maximize system performance, real-world packaging con-

cerns often make it difficult to make the stubs as short as the

designer would like.

Features

n Single +3.3 V Supply

n B/LVDS receiver inputs accept LVPECL signals

n TRI-STATE outputs

n Loss of Signal (LOS) pin detects a non-driven bus

The DS92001 has edge transitions optimized for multidrop

backplanes where the switching frequency is in the 200 MHz

range or less. The output edge rate is critical in some sys-

tems where long stubs may be present, and utilizing a slow

transition allows for longer stub lengths.

n Receiver input threshold

100 mV

n Fast propagation delay of 1.4 ns (typ)

n Low jitter 400 Mbps fully differential data path

n Compatible with BLVDS 10-bit SerDes (40MHz)

n Compatible with ANSI/TIA/EIA-644-A LVDS standard

n Available in SOIC and space saving LLP package

n Industrial Temperature Range

The DS92001, available in the LLP (Leadless Leadframe

Package) package, will allow the receiver inputs to be placed

very close to the main transmission line, thus improving

system performance.

A wide input dynamic range allows the DS92001 to receive

differential signals from LVPECL as well as LVDS sources.

This will allow the device to also fill the role of an LVPECL-

BLVDS translator.

Connection and Block Diagrams

SOIC - Top View

20024702

20024705

Functional Operation

LLP - Top View

BLVDS Inputs

BLVDS Outputs

[IN+] − [IN−]

OUT+

OUT−

VID ≥ 0.1V

VID ≤ −0.1V

Full Fail-safe

OPEN/SHORTor Terminated

20024743

DAP (GND) Pad Not Shown

Ordering Information

Order Number

DS92001TM

DS92001TLD

NS Pkg. No.

Pkg. Type

M08A

SOIC

LLP

LDA08A

DS200247

www.national.com

12 3 4 5 6 7...12

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DS92001TLD 替代型号

型号	品牌	替代类型	描述	数据表
DS92001TLD/NOPB	TI	功能相似	DS92001 3.3V B/LVDS-BLVDS Buffer

与DS92001TLD相关器件

型号	品牌	获取价格	描述	数据表
DS92001TLD/NOPB	TI	获取价格	DS92001 3.3V B/LVDS-BLVDS Buffer
DS92001TLDX	TI	获取价格	暂无描述
DS92001TM	NSC	获取价格	3.3V B/LVDS-BLVDS Buffer
DS92001TMA	TI	获取价格	DS92001 3.3V B/LVDS-BLVDS Buffer
DS92001TMA	NSC	获取价格	3.3V B/LVDS-BLVDS Buffer
DS92001TMA/NOPB	TI	获取价格	DS92001 3.3V B/LVDS-BLVDS Buffer
DS92001TMAX	TI	获取价格	DS92001 3.3V B/LVDS-BLVDS Buffer
DS92001TMAX/NOPB	TI	获取价格	DS92001 3.3V B/LVDS-BLVDS Buffer
DS92CK16	NSC	获取价格	3V BLVDS 1 to 6 Clock Buffer/Bus Transceiver
DS92CK16	MACOM	获取价格	DS92CK16 3V BLVDS 1 to 6 Clock Buffer/Bus Transceiver

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