5秒后页面跳转
捷配首页

Datasheet > 暂无类别数据> DS92001TM
DS92001TM PDF预览

DS92001TM

更新时间： 2024-01-08 11:05:05
品牌 Logo 应用领域
美国国家半导体 - NSC 线路驱动器或接收器驱动程序和接口接口集成电路光电二极管
页数 文件大小 规格书
12页 255K
描述
3.3V B/LVDS-BLVDS Buffer

阅读下载

中文翻译

获取价格

DS92001TM 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：ActiveReach Compliance Code：compliant
ECCN代码：EAR99HTS代码：8542.39.00.01
Factory Lead Time：6 weeks风险等级：5.54
Is Samacsys：N差分输出：YES
驱动器位数：1高电平输入电流最大值：0.00002 A
接口集成电路类型：LINE TRANSCEIVERJESD-30 代码：R-PDSO-G8
JESD-609代码：e3长度：4.9 mm
湿度敏感等级：1功能数量：4
端子数量：8最高工作温度：85 °C
最低工作温度：-40 °C最小输出摆幅：0.25 V
输出特性：3-STATE封装主体材料：PLASTIC/EPOXY
封装代码：SOP封装等效代码：SOP8,.25
封装形状：RECTANGULAR封装形式：SMALL OUTLINE
峰值回流温度（摄氏度）：260电源：3.3 V
认证状态：Not Qualified最大接收延迟：
接收器位数：4座面最大高度：1.75 mm
子类别：Line Driver or Receivers最大压摆率：75 mA
标称供电电压：3.3 V电源电压1-最大：3.6 V
电源电压1-分钟：3 V电源电压1-Nom：3.3 V
表面贴装：YES温度等级：INDUSTRIAL
端子面层：Matte Tin (Sn)端子形式：GULL WING
端子节距：1.27 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED最大传输延迟：2 ns
宽度：3.91 mmBase Number Matches：1

DS92001TM 数据手册

 浏览型号DS92001TM的Datasheet PDF文件第2页浏览型号DS92001TM的Datasheet PDF文件第3页浏览型号DS92001TM的Datasheet PDF文件第4页浏览型号DS92001TM的Datasheet PDF文件第5页浏览型号DS92001TM的Datasheet PDF文件第6页浏览型号DS92001TM的Datasheet PDF文件第7页 
June 2002  
DS92001  
3.3V B/LVDS-BLVDS Buffer  
General Description  
The LOS pin detects a non-driven B/LVDS bus state at the  
input and provides an active LOW output. The LOS pin can  
be tied to the device’s output enable pin (EN) to generate a  
TRI-STATE output state when the input is un-driven. The  
LOS pin can also be used locally to inform the system of the  
bus state.  
The DS92001 B/LVDS-BLVDS Buffer takes a BLVDS input  
signal and provides an BLVDS output signal. In many large  
systems, signals are distributed across backplanes, and one  
of the limiting factors for system speed is the ’stub length’ or  
the distance between the transmission line and the untermi-  
nated receivers on individual cards. Although it is generally  
recognized that this distance should be as short as possible  
to maximize system performance, real-world packaging con-  
cerns often make it difficult to make the stubs as short as the  
designer would like.  
Features  
n Single +3.3 V Supply  
n B/LVDS receiver inputs accept LVPECL signals  
n TRI-STATE outputs  
n Loss of Signal (LOS) pin detects a non-driven bus  
The DS92001 has edge transitions optimized for multidrop  
backplanes where the switching frequency is in the 200 MHz  
range or less. The output edge rate is critical in some sys-  
tems where long stubs may be present, and utilizing a slow  
transition allows for longer stub lengths.  
<
n Receiver input threshold  
100 mV  
n Fast propagation delay of 1.4 ns (typ)  
n Low jitter 400 Mbps fully differential data path  
n Compatible with BLVDS 10-bit SerDes (40MHz)  
n Compatible with ANSI/TIA/EIA-644-A LVDS standard  
n Available in SOIC and space saving LLP package  
n Industrial Temperature Range  
The DS92001, available in the LLP (Leadless Leadframe  
Package) package, will allow the receiver inputs to be placed  
very close to the main transmission line, thus improving  
system performance.  
A wide input dynamic range allows the DS92001 to receive  
differential signals from LVPECL as well as LVDS sources.  
This will allow the device to also fill the role of an LVPECL-  
BLVDS translator.  
Connection and Block Diagrams  
SOIC - Top View  
20024702  
20024705  
Functional Operation  
LLP - Top View  
BLVDS Inputs  
BLVDS Outputs  
[IN+] − [IN−]  
OUT+  
OUT−  
VID ≥ 0.1V  
H
L
L
H
L
VID ≤ −0.1V  
Full Fail-safe  
H
OPEN/SHORTor Terminated  
20024743  
DAP (GND) Pad Not Shown  
Ordering Information  
Order Number  
DS92001TM  
DS92001TLD  
NS Pkg. No.  
Pkg. Type  
M08A  
SOIC  
LLP  
LDA08A  
© 2002 National Semiconductor Corporation  
DS200247  
www.national.com  
1234567...12

中文翻译

下载PDF

与DS92001TM相关器件

型号 品牌 获取价格 描述 数据表
DS92001TMA TI

获取价格

 		DS92001 3.3V B/LVDS-BLVDS Buffer
DS92001TMA NSC

获取价格

 		3.3V B/LVDS-BLVDS Buffer
DS92001TMA/NOPB TI

获取价格

 		DS92001 3.3V B/LVDS-BLVDS Buffer
DS92001TMAX TI

获取价格

 		DS92001 3.3V B/LVDS-BLVDS Buffer
DS92001TMAX/NOPB TI

获取价格

 		DS92001 3.3V B/LVDS-BLVDS Buffer
DS92CK16 NSC

获取价格

 		3V BLVDS 1 to 6 Clock Buffer/Bus Transceiver
DS92CK16 MACOM

获取价格

 		DS92CK16 3V BLVDS 1 to 6 Clock Buffer/Bus Transceiver
DS92CK16 TI

获取价格

 		3V BLVDS 1:6 时钟缓冲器/总线收发器
DS92CK16_06 NSC

获取价格

 		3V BLVDS 1 to 6 Clock Buffer/Bus Transceiver
DS92CK16MDC NSC

获取价格

 		暂无描述

与DS92001TM相关文章

您还可以找


热门产品
PCB打样/小批量
铝基板
BOM智能配单
PCBA制造
钣金
精密CNC
模具注塑
薄膜开关
精选活动
PCBA打样特惠
四六层板品质升级
铝基板品质升级
一体化电子制造
DFM下载
服务支持
企业认证
产品展示
工厂展示
工艺能力
积分商城
关于捷配
捷配简介
企业文化
公司动态
人才招聘
联系我们
帮助中心
下单流程
付款流程
开票流程
常见问题
全球PCB制造服务专线 400-613-0088

工作时间：9:00-21:00

CEO邮箱：ceo@jiepei.com

投诉邮箱：tousu@jiepei.com

捷配网-微信公众号 微信公众号
捷配网-微信公众号 抖音公众号
资质认证：
合作快递：
支付方式：
Copyright © 2024 Jiepei.com Inc. All Rights Reserved. 版权所有:杭州捷配信息科技有限公司 浙公网安备 33010502006866号 浙ICP备10014259号-119 营业执照ICP证