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DS92001TMA

更新时间： 2024-09-26 02:55:11
品牌 Logo 应用领域
美国国家半导体 - NSC 驱动器接口集成电路光电二极管PC
页数 文件大小 规格书
12页 643K
描述
3.3V B/LVDS-BLVDS Buffer

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中文翻译

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DS92001TMA 技术参数

是否Rohs认证： 不符合生命周期：Transferred
包装说明：SOIC-8Reach Compliance Code：not_compliant
ECCN代码：EAR99HTS代码：8542.39.00.01
风险等级：5.34差分输出：YES
驱动器位数：1高电平输入电流最大值：0.00002 A
输入特性：DIFFERENTIAL接口集成电路类型：LINE TRANSCEIVER
接口标准：EIA-644-A; TIA-644-AJESD-30 代码：R-PDSO-G8
JESD-609代码：e0长度：4.9 mm
湿度敏感等级：1功能数量：1
端子数量：8最高工作温度：85 °C
最低工作温度：-40 °C最小输出摆幅：0.25 V
输出特性：3-STATE封装主体材料：PLASTIC/EPOXY
封装代码：SOP封装等效代码：SOP8,.25
封装形状：RECTANGULAR封装形式：SMALL OUTLINE
峰值回流温度（摄氏度）：235电源：3.3 V
认证状态：Not Qualified最大接收延迟：
座面最大高度：1.75 mm子类别：Line Driver or Receivers
最大供电电压：3.6 V最小供电电压：3 V
标称供电电压：3.3 V表面贴装：YES
温度等级：INDUSTRIAL端子面层：Tin/Lead (Sn/Pb)
端子形式：GULL WING端子节距：1.27 mm
端子位置：DUAL处于峰值回流温度下的最长时间：30
最大传输延迟：2 ns宽度：3.9 mm
Base Number Matches：1

DS92001TMA 数据手册

 浏览型号DS92001TMA的Datasheet PDF文件第2页浏览型号DS92001TMA的Datasheet PDF文件第3页浏览型号DS92001TMA的Datasheet PDF文件第4页浏览型号DS92001TMA的Datasheet PDF文件第5页浏览型号DS92001TMA的Datasheet PDF文件第6页浏览型号DS92001TMA的Datasheet PDF文件第7页 
September 2006  
DS92001  
3.3V B/LVDS-BLVDS Buffer  
General Description  
The LOS pin detects a non-driven B/LVDS bus state at the  
input and provides an active LOW output. The LOS pin can  
be tied to the device’s output enable pin (EN) to generate a  
TRI-STATE output state when the input is un-driven. The  
LOS pin can also be used locally to inform the system of the  
bus state.  
The DS92001 B/LVDS-BLVDS Buffer takes a BLVDS input  
signal and provides an BLVDS output signal. In many large  
systems, signals are distributed across backplanes, and one  
of the limiting factors for system speed is the "stub length" or  
the distance between the transmission line and the untermi-  
nated receivers on individual cards. Although it is generally  
recognized that this distance should be as short as possible  
to maximize system performance, real-world packaging con-  
cerns often make it difficult to make the stubs as short as the  
designer would like.  
Features  
n Single +3.3 V Supply  
n B/LVDS receiver inputs accept LVPECL signals  
n TRI-STATE outputs  
n Loss of Signal (LOS) pin detects a non-driven bus  
The DS92001 has edge transitions optimized for multidrop  
backplanes where the switching frequency is in the 200 MHz  
range or less. The output edge rate is critical in some sys-  
tems where long stubs may be present, and utilizing a slow  
transition allows for longer stub lengths.  
<
n Receiver input threshold  
100 mV  
n Fast propagation delay of 1.4 ns (typ)  
n Low jitter 400 Mbps fully differential data path  
n Compatible with BLVDS 10-bit SerDes (40MHz)  
n Compatible with ANSI/TIA/EIA-644-A LVDS standard  
n Available in SOIC and space saving LLP package  
n Industrial Temperature Range  
The DS92001, available in the LLP (Leadless Leadframe  
Package) package, will allow the receiver inputs to be placed  
very close to the main transmission line, thus improving  
system performance.  
A wide input dynamic range allows the DS92001 to receive  
differential signals from LVPECL as well as LVDS sources.  
This will allow the device to also fill the role of an LVPECL-  
BLVDS translator.  
Connection and Block Diagrams  
SOIC - Top View  
20024702  
Functional Operation  
20024705  
BLVDS Inputs  
BLVDS Outputs  
LLP - Top View  
[IN+] − [IN−]  
OUT+  
OUT−  
VID ≥ 0.1V  
H
L
L
H
L
VID ≤ −0.1V  
Full Fail-safe  
H
OPEN/SHORTor Terminated  
Ordering Information  
20024743  
Order Number  
DS92001TMA  
DS92001TLD  
NS Pkg. No.  
Pkg. Type  
M08A  
SOIC  
LLP  
LDA08A  
© 2006 National Semiconductor Corporation  
DS200247  
www.national.com  
1234567...12

中文翻译

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DS92001TMA 替代型号

型号 品牌 替代类型 描述 数据表
DS92001TMA/NOPB TI

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