Datasheet > 驱动程序和接口 > 线路驱动器或接收器> DS92LV010ATMEP

DS92LV010ATMEP

更新时间： 2024-01-22 00:14:52

品牌	Logo	应用领域
美国国家半导体 - NSC		线路驱动器或接收器驱动程序和接口接口集成电路光电二极管
页数	文件大小	规格书
12页	351K
描述
Bus LVDS 3.3/5.0V Single Transceiver

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DS92LV010ATMEP 技术参数

是否无铅：	不含铅	是否Rohs认证：	符合
生命周期：	Active	零件包装代码：	SOIC
包装说明：	SOIC-8	针数：	8
Reach Compliance Code：	unknown	风险等级：	5.31
差分输出：	YES	驱动器位数：	1
输入特性：	DIFFERENTIAL SCHMITT TRIGGER	接口集成电路类型：	LINE TRANSCEIVER
接口标准：	GENERAL PURPOSE	JESD-30 代码：	R-PDSO-G8
JESD-609代码：	e3	长度：	4.9 mm
湿度敏感等级：	1	功能数量：	1
端子数量：	8	最高工作温度：	85 °C
最低工作温度：	-40 °C	封装主体材料：	PLASTIC/EPOXY
封装代码：	SOP	封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE	峰值回流温度（摄氏度）：	260
最大接收延迟：	12 ns	接收器位数：	1
座面最大高度：	1.75 mm	最大供电电压：	3.6 V
最小供电电压：	3 V	标称供电电压：	3.3 V
表面贴装：	YES	技术：	CMOS
温度等级：	INDUSTRIAL	端子面层：	TIN
端子形式：	GULL WING	端子节距：	1.27 mm
端子位置：	DUAL	处于峰值回流温度下的最长时间：	40
最大传输延迟：	5 ns	宽度：	3.9 mm
Base Number Matches：	1

DS92LV010ATMEP 数据手册

OBSOLETE

June 15, 2009

DS92LV010AEP

Bus LVDS 3.3/5.0V Single Transceiver

General Description

Features

The DS92LV010AEP is one in a series of transceivers de-

signed specifically for the high speed, low power proprietary

bus backplane interfaces. The device operates from a single

3.3V or 5.0V power supply and includes one differential line

driver and one receiver. To minimize bus loading the driver

outputs and receiver inputs are internally connected. The log-

ic interface provides maximum flexibility as 4 separate lines

are provided (DIN, DE, RE, and ROUT). The device also fea-

tures flow through which allows easy PCB routing for short

stubs between the bus pins and the connector. The driver has

10 mA drive capability, allowing it to drive heavily loaded

backplanes, with impedance as low as 27 Ohms.

Bus LVDS Signaling (BLVDS)

■

Designed for Double Termination Applications

Balanced Output Impedance

■

Lite Bus Loading 5pF typical

Glitch free power up/down (Driver disabled)

3.3V or 5.0V Operation

±1V Common Mode Range

±100mV Receiver Sensitivity

High Signaling Rate Capability (above 100 Mbps)

Low Power CMOS design

The driver translates between TTL levels (single-ended) to

Low Voltage Differential Signaling levels. This allows for high

speed operation, while consuming minimal power with re-

duced EMI. In addition the differential signaling provides com-

mon mode noise rejection of ±1V.

Product offered in 8 lead SOIC package

Applications

Selected Military Applications

Selected Avionics Applications

The receiver threshold is ±100mV over a ±1V common mode

range and translates the low voltage differential levels to stan-

dard (CMOS/TTL) levels.

ENHANCED PLASTIC

•

Extended Temperature Performance of -40°C to +85°C

Baseline Control - Single Fab & Assembly Site

Process Change Notification (PCN)

Qualification & Reliability Data

Solder (PbSn) Lead Finish is standard

Enhanced Diminishing Manufacturing Sources (DMS)

Support

Ordering Information

PART NUMBER

DS92LV010ATMEP

(Notes 1, 2)

VID PART NUMBER

V62/04740-01

TBD

NS PACKAGE NUMBER (Note 3)

M08A

TBD

Note 1: For the following (Enhanced Plastic) version, check for availability: - DS92LV010ATMXEP Parts listed with an "X" are provided in Tape & Reel and

parts without an "X" are in Rails.

Note 2: FOR ADDITIONAL ORDERING AND PRODUCT INFORMATION, PLEASE VISIT THE ENHANCED PLASTIC WEB SITE AT: www.national.com/

mil

Note 3: Refer to package details under Physical Dimensions

Connection Diagram

20119301

See NS Package Number M08A

TRI-STATE^®is a registered trademark of National Semiconductor Corporation.

201193

www.national.com

201193 Version 3 Revision 1 Print Date/Time: 2009/06/15 11:42:19

12 3 4 5 6 7...12

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与DS92LV010ATMEP相关器件

型号	品牌	描述	获取价格	数据表
DS92LV010ATMX	NSC	IC LINE TRANSCEIVER, PDSO8, SOIC-8, Line Driver or Receiver	获取价格
DS92LV010ATMX	TI	总线 LVDS 3.3/5.0V 单片收发器 \| D \| 8 \| -40 to 85	获取价格
DS92LV010ATMX/NOPB	ROCHESTER	LINE TRANSCEIVER, PDSO8, SOIC-8	获取价格
DS92LV010ATMX/NOPB	TI	总线 LVDS 3.3/5.0V 单片收发器 \| D \| 8 \| -40 to 85	获取价格
DS92LV040	NSC	4 Channel Bus LVDS Transceiver	获取价格
DS92LV040A	NSC	4 Channel Bus LVDS Transceiver	获取价格

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