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DS90CF383BMTX PDF预览

DS90CF383BMTX

更新时间： 2024-09-09 12:54:15
品牌 Logo 应用领域
德州仪器 - TI 线路驱动器或接收器显示器驱动程序和接口接口集成电路光电二极管
页数 文件大小 规格书
16页 958K
描述
3.3V Programmable LVDS Transmitter 24-Bit Flat Panel Display (FPD) Link-65 MHz

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DS90CF383BMTX 技术参数

是否无铅： 含铅是否Rohs认证： 不符合
生命周期：Obsolete零件包装代码：TSSOP
包装说明：TSSOP, TSSOP56,.3,20针数：56
Reach Compliance Code：not_compliantECCN代码：EAR99
HTS代码：8542.39.00.01风险等级：5.43
差分输出：YES驱动器位数：4
输入特性：STANDARD接口集成电路类型：LINE DRIVER
接口标准：EIA-644; TIA-644JESD-30 代码：R-PDSO-G56
JESD-609代码：e0长度：14 mm
湿度敏感等级：2功能数量：1
端子数量：56最高工作温度：70 °C
最低工作温度：-10 °C封装主体材料：PLASTIC/EPOXY
封装代码：TSSOP封装等效代码：TSSOP56,.3,20
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度（摄氏度）：235电源：3.3 V
认证状态：Not Qualified最大接收延迟：
座面最大高度：1.1 mm子类别：Line Driver or Receivers
最大压摆率：60 mA最大供电电压：3.6 V
最小供电电压：3 V标称供电电压：3.3 V
表面贴装：YES技术：CMOS
温度等级：COMMERCIAL端子面层：Tin/Lead (Sn/Pb)
端子形式：GULL WING端子节距：0.5 mm
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：6.1 mmBase Number Matches：1

DS90CF383BMTX 数据手册

 浏览型号DS90CF383BMTX的Datasheet PDF文件第2页浏览型号DS90CF383BMTX的Datasheet PDF文件第3页浏览型号DS90CF383BMTX的Datasheet PDF文件第4页浏览型号DS90CF383BMTX的Datasheet PDF文件第5页浏览型号DS90CF383BMTX的Datasheet PDF文件第6页浏览型号DS90CF383BMTX的Datasheet PDF文件第7页 
DS90CF383B  
www.ti.com  
SNLS178E –JULY 2004–REVISED APRIL 2013  
+3.3V Programmable LVDS Transmitter 24-Bit Flat Panel Display (FPD) Link-65 MHz  
Check for Samples: DS90CF383B  
1
FEATURES  
DESCRIPTION  
The DS90CF383B transmitter converts 28 bits of  
CMOS/TTL data into four LVDS (Low Voltage  
Differential Signaling) data streams. A phase-locked  
transmit clock is transmitted in parallel with the data  
streams over a fifth LVDS link. Every cycle of the  
transmit clock 28 bits of input data are sampled and  
transmitted. At a transmit clock frequency of 65 MHz,  
24 bits of RGB data and 3 bits of LCD timing and  
control data (FPLINE, FPFRAME, DRDY) are  
transmitted at a rate of 455 Mbps per LVDS data  
channel. Using a 65 MHz clock, the data throughput  
is 227 Mbytes/sec. The DS90CF383B is fixed as a  
Falling edge strobe transmitter and will interoperate  
with a Falling edge strobe Receiver (DS90CF386)  
without any translation logic.  
23  
•
No Special Start-up Sequence Required  
Between Clock/Data and /PD Pins. Input Signal  
(Clock and Data) Can be Applied Either Before  
or After the Device is Powered.  
•
•
Support Spread Spectrum Clocking Up to  
100KHz Frequency Modulation & Deviations of  
±2.5% Center Spread or −5% Down Spread.  
"Input Clock Detection" Feature Will Pull All  
LVDS Pairs to Logic Low when Input Clock is  
Missing and When /PD Pin is Logic High.  
•
•
•
18 to 68 MHz Shift Clock Support  
Best–in–Class Set & Hold Times on TxINPUTs  
Tx Power Consumption < 130 mW (typ)  
@65MHz Grayscale  
This chipset is an ideal means to solve EMI and  
cable size problems associated with wide, high speed  
TTL interfaces.  
•
40% Less Power Dissipation Than BiCMOS  
Alternatives  
•
•
Tx Power-down Mode < 60μW (typ)  
Supports VGA, SVGA, XGA and Dual Pixel  
SXGA.  
•
•
•
•
•
•
•
•
Narrow Cus Reduces Cable Size and Cost  
Up to 1.8 Gbps Throughput  
Up to 227 Megabytes/sec Bandwidth  
345 mV (typ) Swing LVDS Devices for Low EMI  
PLL Requires No External Components  
Compatible with TIA/EIA-644 LVDS Standard  
Low Profile 56-Lead TSSOP Package  
Improved Replacement for:  
–
SN75LVDS83, DS90CF383A  
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
2
3
TRI-STATE is a registered trademark of Texas Instruments.  
All other trademarks are the property of their respective owners.  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
Copyright © 2004–2013, Texas Instruments Incorporated  
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DS90CF383BMTX 替代型号

型号 品牌 替代类型 描述 数据表
DS90CF383BMTX/NOPB TI

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