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DS90CF384AMTDX/NOPB PDF预览

DS90CF384AMTDX/NOPB

更新时间: 2024-09-09 19:57:19
品牌 Logo 应用领域
美国国家半导体 - NSC 光电二极管接口集成电路
页数 文件大小 规格书
18页 319K
描述
IC 5 LINE RECEIVER, PDSO56, LOW PROFILE, PLASTIC, TSSOP-56, Line Driver or Receiver

DS90CF384AMTDX/NOPB 技术参数

是否Rohs认证: 符合生命周期:Transferred
包装说明:TSSOP, TSSOP56,.3,20Reach Compliance Code:compliant
ECCN代码:EAR99HTS代码:8542.39.00.01
风险等级:5.26输入特性:DIFFERENTIAL
接口集成电路类型:LINE RECEIVER接口标准:EIA-644; TIA-644
JESD-30 代码:R-PDSO-G56JESD-609代码:e3
长度:14 mm湿度敏感等级:2
功能数量:5端子数量:56
最高工作温度:70 °C最低工作温度:-10 °C
封装主体材料:PLASTIC/EPOXY封装代码:TSSOP
封装等效代码:TSSOP56,.3,20封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH峰值回流温度(摄氏度):260
电源:3.3 V认证状态:Not Qualified
最大接收延迟:接收器位数:5
座面最大高度:1.2 mm子类别:Line Driver or Receivers
最大压摆率:105 mA标称供电电压:3.3 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子面层:Matte Tin (Sn)
端子形式:GULL WING端子节距:0.5 mm
端子位置:DUAL处于峰值回流温度下的最长时间:40
宽度:6.1 mmBase Number Matches:1

DS90CF384AMTDX/NOPB 数据手册

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July 2007  
DS90CF384A/DS90CF364A  
+3.3V LVDS Receiver 24-Bit Flat Panel Display (FPD) Link  
—65 MHz, +3.3V LVDS Receiver 18-Bit Flat Panel Display  
(FPD) Link—65 MHz  
This chipset is an ideal means to solve EMI and cable size  
problems associated with wide, high speed TTL interfaces.  
General Description  
The DS90CF384A receiver converts the four LVDS data  
streams (Up to 1.8 Gbps throughput or 227 Megabytes/sec  
bandwidth) back into parallel 28 bits of CMOS/TTL data (24  
Features  
20 to 65 MHz shift clock support  
bits of RGB and 4 bits of Hsync, Vsync, DE and CNTL). Also  
available is the DS90CF364A that converts the three LVDS  
data streams (Up to 1.3 Gbps throughput or 170 Megabytes/  
sec bandwidth) back into parallel 21 bits of CMOS/TTL data  
(18 bits of RGB and 3 bits of Hsync, Vsync and DE). Both  
Receivers' outputs are Falling edge strobe. A Rising edge or  
Falling edge strobe transmitter (DS90C383A/DS90C363A)  
will interoperate with a Falling edge strobe Receiver without  
any translation logic.  
50% duty cycle on receiver output clock  
Best–in–Class Set & Hold Times on RxOUTPUTs  
Rx power consumption <142 mW (typ) @65MHz  
Grayscale  
Rx Power-down mode <200μW (max)  
ESD rating >7 kV (HBM), >700V (EIAJ)  
Supports VGA, SVGA, XGA and Dual Pixel SXGA.  
PLL requires no external components  
The DS90CF384A / DS90CF364A devices are enhanced  
over prior generation receivers and provided a wider data  
valid time on the receiver output.  
Compatible with TIA/EIA-644 LVDS standard  
Low profile 56-lead or 48-lead TSSOP package  
The DS90CF384A is also offered in a 64 ball, 0.8mm fine pitch  
ball grid array (FBGA) package which provides a 44 % re-  
duction in PCB footprint compared to the 56L TSSOP pack-  
age.  
DS90CF384A is also available in a 64 ball, 0.8mm fine  
pitch ball grid array (FBGA) package  
Block Diagrams  
DS90CF384A  
DS90CF364A  
10087027  
10087028  
Order Number DS90CF384AMTD or DS90CF384ASLC  
Order Number DS90CF364AMTD  
See NS Package Number MTD48  
See NS Package Number MTD56 or SLC64A  
TRI-STATE® is a registered trademark of National Semiconductor Corporation.  
© 2007 National Semiconductor Corporation  
100870  
www.national.com  

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