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DS90CF384

更新时间： 2024-11-08 22:50:51

品牌	Logo	应用领域
美国国家半导体 - NSC		显示器光电二极管
页数	文件大小	规格书
20页	368K
描述
+3.3V Programmable LVDS Transmitter 24-Bit Flat Panel Display (FPD) Link-65 MHz, +3.3V LVDS Receiver 24-Bit Flat Panel Display (FPD) Link-65 MHz

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DS90CF384 数据手册

November 2000

DS90C383/DS90CF384

+3.3V Programmable LVDS Transmitter 24-Bit Flat Panel

Display (FPD) Link—65 MHz, +3.3V LVDS Receiver

24-Bit Flat Panel Display (FPD) Link—65 MHz

General Description

Features

n 20 to 65 MHz shift clock support

n Programmable transmitter (DS90C383) strobe select

(Rising or Falling edge strobe)

The DS90C383 transmitter converts 28 bits of LVCMOS/

LVTTL data into four LVDS (Low Voltage Differential Signal-

ing) data streams. A phase-locked transmit clock is transmit-

ted in parallel with the data streams over a fifth LVDS link.

Every cycle of the transmit clock 28 bits of input data are

sampled and transmitted. The DS90CF384 receiver con-

verts the LVDS data streams back into 28 bits of LVCMOS/

LVTTL data. At a transmit clock frequency of 65 MHz, 24 bits

of RGB data and 3 bits of LCD timing and control data

(FPLINE, FPFRAME, DRDY) are transmitted at a rate of 455

Mbps per LVDS data channel. Using a 65 MHz clock, the

data throughputs is 227 Mbytes/sec. The transmitter is of-

fered with programmable edge data strobes for convenient

interface with a variety of graphics controllers. The transmit-

ter can be programmed for Rising edge strobe or Falling

edge strobe through a dedicated pin. A Rising edge trans-

n Single 3.3V supply

n Chipset (Tx + Rx) power consumption 250 mW (typ)

n Power-down mode ( 0.5 mW total)

n Single pixel per clock XGA (1024x768) ready

n Supports VGA, SVGA, XGA and higher addressability.

n Up to 227 Megabytes/sec bandwidth

n Up to 1.8 Gbps throughput

n Narrow bus reduces cable size and cost

n 290 mV swing LVDS devices for low EMI

n PLL requires no external components

n Low profile 56-lead TSSOP package.

n Also available in a 64 ball, 0.8mm fine pitch ball grid

array (FBGA) package

mitter will inter-operate with

a Falling edge receiver

(DS90CF384) without any translation logic. Both devices are

also offered in a 64 ball, 0.8mm fine pitch ball grid array

(FBGA) package which provides a 44 % reduction in PCB

footprint compared to the TSSOP package.

n Falling edge data strobe Receiver

n Compatible with TIA/EIA-644 LVDS standard

n ESD rating 7 kV

n Operating Temperature: −40˚C to +85˚C

This chipset is an ideal means to solve EMI and cable size

problems associated with wide, high speed TTL interfaces.

Block Diagrams

Typical Application

DS012887-2

TRI-STATE^®is a registered trademark of National Semiconductor Corporation.

DS012887

www.national.com

12 3 4 5 6 7...20

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与DS90CF384相关器件

型号	品牌	获取价格	描述	数据表
DS90CF384A	NSC	获取价格	+3.3V LVDS Receiver 24-Bit Flat Panel Display
DS90CF384A	TI	获取价格	DS90CF384A/DS90CF364A 3.3V LVDS Receiver 24-Bit Flat Panel Display (FPD) Link - 65 MHz, 3.
DS90CF384AMDA	NSC	获取价格	IC LINE RECEIVER, UUC, DIE, Line Driver or Receiver
DS90CF384AMTD	NSC	获取价格	+3.3V LVDS Receiver 24-Bit Flat Panel Display
DS90CF384AMTD/NOPB	ROCHESTER	获取价格	QUAD LINE RECEIVER, PDSO56, TSSOP-56
DS90CF384AMTD/NOPB	TI	获取价格	+3.3V LVDS 接收器 24 位平板显示器 (FPD) 链路 - 65MHz \| D
DS90CF384AMTDX	TI	获取价格	DS90CF384A/DS90CF364A 3.3V LVDS Receiver 24-Bit Flat Panel Display (FPD) Link - 65 MHz, 3.
DS90CF384AMTDX	NSC	获取价格	IC QUAD LINE RECEIVER, PDSO56, TSSOP-56, Line Driver or Receiver
DS90CF384AMTDX/NOPB	TI	获取价格	+3.3V LVDS 接收器 24 位平板显示器 (FPD) 链路 - 65MHz \| D
DS90CF384AMTDX/NOPB	NSC	获取价格	IC 5 LINE RECEIVER, PDSO56, LOW PROFILE, PLASTIC, TSSOP-56, Line Driver or Receiver

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