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DS90CF384MTDX PDF预览

DS90CF384MTDX

更新时间: 2024-09-09 13:07:27
品牌 Logo 应用领域
德州仪器 - TI 显示器光电二极管
页数 文件大小 规格书
19页 1098K
描述
QUAD LINE RECEIVER, PDSO56, LOW PROFILE, PLASTIC, TSSOP-56

DS90CF384MTDX 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Obsolete零件包装代码:TSSOP
包装说明:TSSOP, TSSOP56,.3,20针数:56
Reach Compliance Code:not_compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.26
输入特性:DIFFERENTIAL接口集成电路类型:LINE RECEIVER
接口标准:EIA-644; TIA-644JESD-30 代码:R-PDSO-G56
JESD-609代码:e0长度:14 mm
湿度敏感等级:2功能数量:4
端子数量:56最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP封装等效代码:TSSOP56,.3,20
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度(摄氏度):235电源:3.3 V
认证状态:Not Qualified最大接收延迟:
接收器位数:4座面最大高度:1.2 mm
子类别:Line Driver or Receivers最大压摆率:105 mA
标称供电电压:3.3 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:GULL WING
端子节距:0.5 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:6.1 mm
Base Number Matches:1

DS90CF384MTDX 数据手册

 浏览型号DS90CF384MTDX的Datasheet PDF文件第2页浏览型号DS90CF384MTDX的Datasheet PDF文件第3页浏览型号DS90CF384MTDX的Datasheet PDF文件第4页浏览型号DS90CF384MTDX的Datasheet PDF文件第5页浏览型号DS90CF384MTDX的Datasheet PDF文件第6页浏览型号DS90CF384MTDX的Datasheet PDF文件第7页 
DS90CF364A, DS90CF384A  
www.ti.com  
SNLS040I JUNE 2000REVISED APRIL 2013  
DS90CF384A/DS90CF364A +3.3V LVDS Receiver 24-Bit Flat Panel Display (FPD) Link - 65  
MHz, +3.3V LVDS Receiver 18-Bit Flat Panel Display (FPD) Link - 65 MHz  
Check for Samples: DS90CF364A, DS90CF384A  
1
FEATURES  
DESCRIPTION  
The DS90CF384A receiver converts the four LVDS  
data streams (Up to 1.8 Gbps throughput or 227  
Megabytes/sec bandwidth) back into parallel 28 bits  
of CMOS/TTL data (24 bits of RGB and 4 bits of  
Hsync, Vsync, DE and CNTL). Also available is the  
DS90CF364A that converts the three LVDS data  
streams (Up to 1.3 Gbps throughput or 170  
Megabytes/sec bandwidth) back into parallel 21 bits  
of CMOS/TTL data (18 bits of RGB and 3 bits of  
Hsync, Vsync and DE). Both Receivers' outputs are  
Falling edge strobe. A Rising edge or Falling edge  
strobe transmitter (DS90C383A/DS90C363A) will  
interoperate with a Falling edge strobe Receiver  
without any translation logic.  
2
20 to 65 MHz Shift Clock Support  
50% Duty Cycle on Receiver Output Clock  
Best-in-Class Set & Hold Times on  
RxOUTPUTs  
Rx Power Consumption <142 mW (typ)  
@65MHz Grayscale  
Rx Power-down Mode <200μW (max)  
ESD Rating >7 kV (HBM), >700V (EIAJ)  
Supports VGA, SVGA, XGA and Dual Pixel  
SXGA.  
PLL Requires no External Components  
Compatible with TIA/EIA-644 LVDS Standard  
Low Profile 56-lead or 48-lead Packages  
The DS90CF384A  
/ DS90CF364A devices are  
enhanced over prior generation receivers and  
provided a wider data valid time on the receiver  
output.  
This chipset is an ideal means to solve EMI and  
cable size problems associated with wide, high speed  
TTL interfaces.  
BLOCK DIAGRAMS  
Figure 1. DS90CF384A  
DGG-56 (TSSOP)  
Figure 2. DS90CF364A  
DGG-48 (TSSOP)  
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
All trademarks are the property of their respective owners.  
2
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
Copyright © 2000–2013, Texas Instruments Incorporated  

DS90CF384MTDX 替代型号

型号 品牌 替代类型 描述 数据表
DS90CF384MTD NSC

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+3.3V Programmable LVDS Transmitter 24-Bit Flat Panel Display (FPD) Link-65 MHz, +3.3V LVD

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