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DS80C390-QCR PDF预览

DS80C390-QCR

更新时间: 2024-11-22 22:49:07
品牌 Logo 应用领域
达拉斯 - DALLAS 微处理器
页数 文件大小 规格书
58页 5482K
描述
Dual CAN High-Speed Microprocessor

DS80C390-QCR 数据手册

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PRELIMINARY  
DS80C390  
Dual CAN High-Speed  
Microprocessor  
www.dalsemi.com  
FEATURES  
§ 80C52 compatible  
PIN ASSIGNMENT  
48  
33  
-
-
-
-
8051 instruction-set compatible  
Four 8-bit I/O ports  
Three 16-bit timer/counters  
256 bytes scratchpad RAM  
49  
32  
§ High-Speed Architecture  
DS80C390  
-
-
-
-
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4 clocks/machine cycle (8051=12)  
Runs DC to 40 MHz clock rates  
Frequency multiplier reduces EMI  
Single-cycle instruction in 100 ns  
16/32-bit math coprocessor  
17  
64  
§ 4 kB internal SRAM usable as  
program/data/stack memory  
1
16  
64-PIN QFP  
§ Enhanced memory architecture  
-
-
-
-
Addresses up to 4 MB external  
Defaults to true 8051 memory compatibility  
User-enabled 22-bit program/data counter  
16-Bit/22-bit paged/22-bit contiguous  
modes  
9
1
61  
10  
60  
-
User-selectable multiplexed / non-  
multiplexed memory interface  
Optional 10 bit stack pointer  
DS80C390  
-
§ Two full-function CAN 2.0B controllers  
-
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15 message centers per controller  
Standard 11-bit or extended 29-bit  
identification modes  
26  
44  
27  
43  
-
Supports DeviceNet, SDS, and higher layer  
68-PIN PLCC  
CAN protocols  
-
-
Disables transmitter during autobaud  
SIESTA low power mode  
§ Two full-duplex hardware serial ports  
§ Programmable IrDA clock  
§ High integration controller includes  
-
-
-
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Power-fail reset  
Early-warning power-fail interrupt  
Programmable watchdog timer  
Oscillator-fail detection  
§ 16 total interrupt sources with 6 external  
§ Available in 64-pin QFP, 68-pin PLCC  
1 of 58  
110199  

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