19-4658; Rev 7; 6/09
EVALUATION KIT AVAILABLE
DS80C400
Network Microcontroller
www.maxim-ic.com
GENERAL DESCRIPTION
FEATURES
The DS80C400 network microcontroller offers the highest
integration available in an 8051 device. Peripherals include
a 10/100 Ethernet MAC, three serial ports, a CAN 2.0B
controller, 1-Wire® Master, and 64 I/O pins.
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.
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High-Performance Architecture
Single 8051 Instruction Cycle in 54ns
DC to 75MHz Clock Rate
Flat 16MB Address Space
Four Data Pointers with Auto-Increment/
Decrement and Select-Accelerate Data Movement
16/32-Bit Math Accelerator
To enable access to the network, a full application-
accessible TCP IPv4/6 network stack and OS are provided
in the ROM. The network stack supports up to 32
simultaneous TCP connections and can transfer up to
5Mbps through the Ethernet MAC. Its maximum system-
clock frequency of 75MHz results in a minimum instruction
cycle time of 54ns. Access to large program or data
memory areas is simplified with a 24-bit addressing
scheme that supports up to 16MB of contiguous memory.
Multitiered Networking and I/O
10/100 Ethernet Media Access Controller (MAC)
CAN 2.0B Controller
1-Wire Net Controller
Three Full-Duplex Hardware Serial Ports
Up to Eight Bidirectional 8-Bit Ports (64 Digital I/O
Pins)
To accelerate data transfers between the microcontroller
and memory, the DS80C400 provides four data pointers,
each of which can be configured to automatically increment
or decrement upon execution of certain data pointer-related
instructions. The DS80C400’s hardware math accelerator
further increases the speed of 32-bit and 16-bit multiply
and divide operations as well as high-speed shift,
normalization, and accumulate functions.
Robust ROM Firmware
Supports Network Boot Over Ethernet Using DHCP
and TFTP
Full, Application-Accessible TCP/IP Network Stack
Supports IPv4 and IPv6
Implements UDP, TCP, DHCP, ICMP, and IGMP
Preemptive, Priority-Based Task Scheduler
MAC Address can Optionally be Acquired from IEEE-
Registered DS2502-E48
The High-Speed Microcontroller User’s Guide and the High-Speed
Microcontroller User’s Guide: Network Microcontroller Supplement
should be used in conjunction with this data sheet. Download
both at: www.maxim-ic.com/user_guides.
.
10/100 Ethernet MAC
Flexible IEEE 802.3 MII (10/100Mbps) and ENDEC
(10Mbps) Interfaces Allow Selection of PHY
Low-Power Operation
Ultra-Low-Power Sleep Mode with Magic Packet®
and Wake-Up Frame Detection
APPLICATIONS
Industrial Control/Automation Data Converters (Serial-
to-Ethernet, CAN-to-
8kB On-Chip Tx/Rx Packet Data Memory with Buffer
Control Unit Reduces Load on CPU
Half- or Full-Duplex Operation with Flow Control
Multicast/Broadcast Address Filtering with VLAN
Support
Environmental Monitoring
Ethernet)
Network Sensors
Remote Data Collection
Equipment
Vending
.
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Full-Function CAN 2.0B Controller
15 Message Centers
Transaction/Payment
Terminals
Home/Office Automation
Supports Standard (11-Bit) and Extended (29-Bit)
Identifiers and Global Masks
Media Byte Filtering to Support DeviceNet™, SDS, and
Higher Layer CAN Protocols
ORDERING INFORMATION
PART
TEMP RANGE
PIN-PACKAGE
Auto-Baud Mode and SIESTA Low-Power Mode
Integrated Primary System Logic
16 Total Interrupt Sources with Six External
Four 16-Bit Timer/Counters
DS80C400-FNY
DS80C400-FNY+
-40°C to +85°C 100 LQFP
-40°C to +85°C 100 LQFP
2x/4x Clock Multiplier Reduces Electromagnetic
Interference (EMI)
Programmable Watchdog Timer
Oscillator-Fail Detection
+Denotes a lead(Pb)-free/RoHS-compliant package.
1-Wire is a registered trademark of Maxim Integrated Products, Inc.
Magic Packet is a registered trademark of Advanced Micro Devices, Inc.
DeviceNet is a trademark of Open DeviceNet Vendor Association, Inc.
Programmable IrDA Clock
Features continued on page 32.
Pin Configuration appears at end of data sheet.
Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device
may be simultaneously available through various sales channels. For information about device errata, click here: www.maxim-ic.com/errata.
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