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DS80C410 PDF预览

DS80C410

更新时间: 2024-09-28 22:49:07
品牌 Logo 应用领域
达拉斯 - DALLAS 微控制器以太网
页数 文件大小 规格书
102页 2097K
描述
Network Microcontrollers with Ethernet and CAN

DS80C410 数据手册

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DS80C410/DS80C411  
Network Microcontrollers with  
Ethernet and CAN  
www.maxim-ic.com  
GENERAL DESCRIPTION  
FEATURES  
The DS80C410/DS80C411 network microcontrollers offer  
the highest integration available in an 8051 device.  
Peripherals include a 10/100 Ethernet MAC, three serial  
ports, an optional CAN 2.0B controller, 1-Wire® Master,  
and 64 I/O pins. The DS80C410 and DS80C411 also  
include 64kBytes internal SRAM for user application  
storage and network stack.  
CꢀSHiingghle-P8e0r5f1orImnsatrnuccetioAnrCcyhcitleecintu5r4ens  
DC to 75MHz Clock Rate  
Flat 16MB Address Space  
Four Data Pointers with Auto-Increment/  
Decrement and Select-Accelerate Data Movement  
16/32-Bit Math Accelerator  
CꢀM10u/1lt0it0ieErtehderNneettwMoedrkiainAgccaensds IC/Oontroller (MAC)  
To enable access to the network, a full application-  
accessible TCP IPv4/6 network stack and OS are provided  
in the ROM. The network stack supports up to 32  
simultaneous TCP connections and can transfer up to  
5Mbps through the Ethernet MAC. Its maximum system-  
clock frequency of 75MHz results in a minimum instruction  
cycle time of 54ns. Access to large program or data  
memory areas is simplified with a 24-bit addressing  
scheme that supports up to 16MB of contiguous memory.  
To accelerate data transfers between the microcontroller  
and memory, the DS80C410 and DS80C411 provide four  
data pointers, each of which can be configured to  
automatically increment or decrement upon execution of  
certain data pointer-related instructions. High-speed shift,  
normalization, accumulate functions and 32-bit/16-bit  
multiply and divide operations are optimized by the  
DS80C410/DS80C411 hardware math accelerator.  
Optional CAN 2.0B Controller  
1-Wire Net Controller  
Three Full-Duplex Hardware Serial Ports  
Up to Eight Bidirectional 8-Bit Ports (64 Digital I/O Pins)  
CꢀSRuopbpuosrttsRNOeMtwoFrikrmBowoatrOever Ethernet Using DHCP and  
TFTP  
Full, Application-Accessible TCP/IP Network Stack  
Supports IPv4 and IPv6  
Implements UDP, TCP, DHCP, ICMP, and IGMP  
Preemptive, Priority-Based Task Scheduler  
MAC Address can Optionally be Acquired from IEEE-  
Registered DS2502-E48  
CꢀF10le/x1i0b0leEIEthEeErn80e2t.M3 aMcII (10/100Mbps) and ENDEC  
(10Mbps) Interfaces Allow Selection of PHY  
Low-Power Operation  
The High-Speed Microcontroller User’s Guide and the High-Speed  
Microcontroller User’s Guide: Network Microcontroller Supplement  
should be used in conjunction with this data sheet. Download  
both at: www.maxim-ic.com/user_guides.  
Ultra-Low-Power Sleep Mode with Magic Packet®  
and Wake-Up Frame Detection  
8kB On-Chip Tx/Rx Packet Data Memory with Buffer  
Control Unit Reduces Load on CPU  
Half- or Full-Duplex Operation with Flow Control  
Multicast/Broadcast Address Filtering with VLAN  
Support  
APPLICATIONS  
Data Converters (Serial-to-  
Ethernet, CAN-to-  
Ethernet)  
Industrial Control/Automation  
Environmental Monitoring  
Network Sensors  
Vending  
Features continued on page 34.  
Pin Configuration appears at end of data sheet.  
Selector Guide appears at end of data sheet.  
Remote Data-Collection  
Equipment  
Home/Office Automation  
Transaction/Payment  
ORDERING INFORMATION  
Terminals  
PART  
TEMP RANGE  
-40°C to +85°C  
-40°C to +85°C  
-40°C to +85°C  
-40°C to +85°C  
PIN-PACKAGE  
100 LQFP  
1-Wire is a registered trademark of Dallas Semiconductor Corp.  
Magic Packet is a registered trademark of Advanced Micro  
Devices, Inc.  
DS80C410-FNY  
DS80C410-FNY+  
DS80C411-FNY  
DS80C411-FNY+  
100 LQFP  
100 LQFP  
100 LQFP  
+ Denotes lead-free/RoHS-compliant device.  
Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device  
may be simultaneously available through various sales channels. For information about device errata, click here: www.maxim-ic.com/errata.  
1 of 102  
REV: 060805  

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