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DS31256_V01 PDF预览

DS31256_V01

更新时间: 2024-02-02 15:45:46
品牌 Logo 应用领域
美信 - MAXIM /
页数 文件大小 规格书
183页 1218K
描述
256-Channel, High-Throughput HDLC Controller

DS31256_V01 数据手册

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DEMO KIT AVAILABLE  
DS31256  
256-Channel, High-Throughput  
HDLC Controller  
www.maxim-ic.com  
GENERAL DESCRIPTION  
FEATURES  
The DS31256 Envoy is a 256-channel HDLC 256 Independent, Bidirectional HDLC  
controller that can handle up to 60 T1 or 64 E1  
Channels  
data streams or two T3 data streams. Each of the Up to 132Mbps Full-Duplex Throughput  
16 physical ports can handle one, two, or four Supports Up to 60 T1 or 64 E1 Data Streams  
T1 or E1 data streams. The DS31256 is 16 Physical Ports (16 Tx and 16 Rx) That  
composed of the following blocks: Layer 1,  
HDLC processing, FIFO, DMA, PCI bus, and  
local bus.  
Can Be Independently Configured for  
Channelized or Unchannelized Operation  
Three Fast (52Mbps) Ports; Other Ports  
Capable of Speeds Up to 10Mbps  
(Unchannelized)  
There are 16 HDLC engines (one for each port)  
that are each capable of operating at speeds up Channelized Ports Can Each Handle One,  
to 8.192Mbps in channelized mode and up to  
10Mbps in unchannelized mode. The DS31256 Per-Channel DS0 Loopbacks in Both  
Envoy also has three fast HDLC engines that Directions  
Two, or Four T1 or E1 Lines  
only reside on Ports 0, 1, and 2. They are Over-Subscription at the Port Level  
capable of operating at speeds up to 52Mbps.  
Transparent Mode Supported  
On-Board Bit Error-Rate Tester (BERT)  
with Automatic Error Insertion Capability  
BERT Function Can Be Assigned to Any  
HDLC Channel or Any Port  
APPLICATIONS  
Channelized and Clear-Channel  
(Unchannelized) T1/E1 and T3/E3  
Routers with Multilink PPP Support  
High-Density Frame-Relay Access  
xDSL Access Multiplexers (DSLAMs)  
Triple HSSI  
Large 16kB FIFO in Both Receive and  
Transmit Directions  
Efficient Scatter/Gather DMA Maximizes  
Memory Efficiency  
Receive Data Packets are Time-Stamped  
Transmit Packet Priority Setting  
V.54 Loopback Code Detector  
Local Bus Allows for PCI Bridging or Local  
Access  
High-Density V.35  
SONET/SDH EOC/ECC Termination  
ORDERING INFORMATION  
PART  
DS31256  
DS31256+  
TEMP RANGE PIN-PACKAGE  
Intel or Motorola Bus Signals Supported  
Backward Compatibility with DS3134  
33MHz 32-Bit PCI (V2.1) Interface  
3.3V Low-Power CMOS with 5V Tolerant  
I/O  
0°C to +70°C  
256 PBGA  
0°C to +70°C  
256 PBGA  
+Denotes lead-free/RoHS-compliant package.  
JTAG Support IEEE 1149.1  
256-Pin Plastic BGA (27mm x 27mm)  
Features continued on page 6.  
Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device  
may be simultaneously available through various sales channels. For information about device errata, click here: www.maxim-ic.com/errata.  
1 of 183  
REV: 012506  

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